Hardware Engineer, RTL Lead

Job Title

Hardware Engineer, RTL Lead

Role Summary

Lead RTL design and implementation for Normal's thermodynamic hardware, owning RTL from microarchitecture through tapeout. Work closely with architecture, verification, and physical design teams to deliver synthesizable SystemVerilog and meet PPA and timing targets.

As a team lead you will define RTL methodology, hire and mentor engineers, organize work to meet schedule, and participate in architecture and design decisions.

Experience Level

Senior - experienced in leading RTL teams and delivering silicon through tapeout. Specific years of experience not specified.

Responsibilities

The role combines technical ownership and team leadership; primary responsibilities include:

• Lead and organize the RTL design team; set standards and drive execution.
• Write and own synthesizable SystemVerilog across datapath, control, and memory interfaces; define and enforce RTL coding standards.
• Translate high-level specifications into implementable microarchitectures with architects.
• Collaborate with verification to review plans, assist on debug, and close coverage using simulation and formal methods.
• Work with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.
• Participate in design and architecture reviews and contribute to architectural decisions.
• Prepare tapeout criteria, support tapeout signoff, and assist with post-silicon bring-up as needed.

Requirements

Must-have:

• Proven experience leading an RTL design team through multiple tapeouts, including block and top-level work.
• Hands-on production experience writing SystemVerilog and closing RTL through synthesis and place-and-route.
• Experience with datapaths, pipelines, or custom logic where microarchitecture was developed during design.
• Strong debugging skills across simulation, waveform analysis, and formal counterexamples.
• Ability to work directly with architects and physical designers.

Nice-to-have:

• Experience at an AI chip company with tightly coupled design and verification.
• Experience with interfaces such as PCIe, Ethernet, and memory devices.
• FPGA experience and familiarity with AI-assisted RTL or EDA tooling.
• Exposure to physical-design constraints, floorplanning, or timing-driven RTL development.

Education Requirements

Not specified.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.