Hardware Engineer, RTL

Job Title

Hardware Engineer, RTL

Role Summary

Design and verify synthesizable RTL for Normal Computing's novel thermodynamic ASICs. Work across microarchitecture, verification, and physical design to take blocks from specification through tapeout and post-silicon bring-up.

The role sits on the RTL/design team collaborating closely with architects, verification engineers, and physical designers to deliver production silicon.

Experience Level

Mid-level. Candidates are expected to have industry ASIC/SoC experience and at least one tapeout; specific years of experience are not stated.

Responsibilities

You will own RTL design and delivery across the project lifecycle.

• Write and own synthesizable SystemVerilog RTL across datapath, control, and memory interface blocks.
• Translate high-level specifications into implementable microarchitecture with architects.
• Partner with verification to review plans, assist on debug, and help close coverage.
• Collaborate with physical design on timing closure, floorplanning constraints, and DFT considerations.
• Participate in design reviews and contribute to architectural decisions.
• Support tapeout preparation, integration, and post-silicon bring-up as required.

Requirements

Must-have technical skills and experience.

• Production experience writing RTL in SystemVerilog and taking it through synthesis and place-and-route.
• Proven ability to close verification coverage and support debug (simulation, waveforms, formal counterexamples).
• At least one tapeout (any node or company size).
• Experience with datapaths, pipelines, or custom logic where microarchitecture was developed iteratively.
• Ability to work directly with architects and physical designers.
• Industry experience in ASIC or SoC design.

Nice-to-have:

• Experience at an AI chip company where design and verification were tightly coupled.
• Open-source RTL contributions (e.g., Chipyard, OpenTitan, CVA6) or familiarity with RISC-V or other open ISAs.
• Experience with AI-assisted RTL or EDA tooling.
• Exposure to physical design constraints, floorplanning, or timing-driven RTL development.

Education Requirements

Not specified.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.