Hardware Engineer, Physical Design
Normal ComputingJob Title
Hardware Engineer, Physical Design
Role Summary
Lead end-to-end physical implementation and signoff for advanced ASICs, collaborating with RTL, architecture, verification, and DFT teams to achieve aggressive power, performance, and area (PPA) targets. This role focuses on netlist-to-GDSII flow, timing closure, and physical verification in fast iteration cycles.
On-site locations include New York City; London; Zurich; Silicon Valley; Copenhagen.
Experience Level
Mid-level — typically 3+ years of backend physical-design and tapeout experience; tapeout-proven execution expected.
Responsibilities
Primary responsibilities include driving physical implementation, timing signoff, and physical verification to tapeout.
- Lead full netlist-to-GDSII physical design flow: floorplanning, power-grid design, placement, CTS, and P&R.
- Own static timing analysis (STA), create/validate timing constraints, and achieve timing closure across corners and modes.
- Optimize power, performance, and area; address IR/EM, crosstalk, and signal-integrity issues.
- Execute physical signoff checks (DRC, LVS, ERC, antenna fixes) and manage final stream-out and tapeout checklists.
- Collaborate with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, and pin assignments.
- Support post-silicon physical debugging and bring-up as needed.
Requirements
Clear must-haves and relevant technical skills.
- At least 3+ successful tapeouts from netlist to signoff (tapeout-proven execution).
- Hands-on experience with industry-standard PD and signoff tools (examples: Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre).
- Strong skills in STA, timing-closure, and backend debugging (timing bottlenecks, IR/EM, crosstalk, DRC/LVS issues).
- Proven ability to work cross-functionally to influence physical feasibility, floorplanning, and pin placement.
- Experience with scripting for automation (TCL/Python) is preferred.
Nice-to-have:
- Experience at AI or high-performance compute (HPC) chip startups with tight iteration cycles.
- Custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (chiplets, 2.5D/3D).
- Experience developing or maintaining automated PD scripting frameworks.
Education Requirements
Not specified.
Normal Computing is an equal opportunity employer and values diversity. Reasonable accommodations for applicants with disabilities can be requested via accommodations@normalcomputing.com.
About the Company
Company: Normal Computing
Headquarters: New York, NY, USA
Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.
