Hardware Engineer, Performance Modeling

Job Title

Hardware Engineer, Performance Modeling

Role Summary

Build and maintain the transaction-level model (TLM) that links RTL, prototypes, and physical results to system-level performance predictions. Work with architecture, hardware design, and DV teams to convert model and hardware data into calibrated latency, bandwidth, energy, and utilization parameters used for design decisions.

Experience Level

Mid-level - 5+ years of performance modeling experience, preferably in a semiconductor company.

Responsibilities

Key responsibilities include developing accurate, high-performance models and using them to guide architecture and design trade-offs.

• Design, implement, and maintain cycle-accurate or approximate transaction-level models (SystemC, C++, or Python) for compute tiles, memory hierarchy, and interconnect.
• Ensure models run on real workloads: balance simulation speed with fidelity to support production decisions.
• Correlate TLM outputs with RTL, FPGA prototypes, synthesis, and physical design to generate calibrated parameters (latency, bandwidth, energy, utilization, occupancy).
• Deliver the TLM as a verification reference (scoreboards and performance checks) and collaborate with DV and RTL teams to align behavior.
• Plan modeling tasks against the hardware roadmap and run sensitivity studies to produce actionable recommendations for architecture and hardware teams.

Requirements

Must-have skills and experience followed by desirable qualifications.

• 5+ years of performance or architecture-level modeling experience at a semiconductor company.
• Proven ability to translate architecture descriptions into performant modeling code.
• Experience with modeling languages and techniques (SystemC, C++, Python preferred).
• Experience analyzing latency, bandwidth, energy, occupancy, and utilization.
• Excellent written and verbal communication skills for cross-functional collaboration.
• Nice-to-have: experience with AI acceleration hardware, AccelForge/Timeloop/Accelergy/CACTI/McPAT/gem5-like tools, DV methodology, memory interfaces (LPDDR, HBM, DDR), analog/mixed-signal exposure, or use of LLMs/agentic tools in development workflows.

Education Requirements

Not specified.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.