Hardware Engineer, FPGA

Job Title

Hardware Engineer, FPGA

Role Summary

The FPGA Design Engineer will bridge RTL and physical silicon: implement complex ASIC RTL on FPGA platforms for pre-silicon validation and early software development, and build test infrastructure for post-silicon bring-up and characterization.

You will work with silicon, EDA, and research teams to select platforms, implement RTL, debug in the lab, and develop the software tooling around hardware.

Experience Level

Mid-level (experienced engineer). Specific years of experience not stated; role expects proven industry FPGA/ASIC prototyping experience.

Responsibilities

Key responsibilities include FPGA platform bring-up, RTL adaptation, IP integration, high-speed I/O validation, and building test infrastructure and automation.

• Select, procure, and bring up FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class or custom boards).
• Adapt and implement complex ASIC RTL onto FPGA targets, handling multi-clock domains, CDC, and timing closure.
• Integrate in-house designs with third-party/vendor IP; act as AMD/Xilinx ecosystem expert (Vivado IP Integrator, transceivers, memory controllers).
• Design, implement, and validate high-speed interfaces with a focus on PCIe for server accelerator cards.
• Build FPGA-based tester designs for silicon bring-up, device characterization, and automated test environments.
• Develop hardware-software stack: Python/C++ hardware abstraction, register-map generation, automated build and regression flows.
• Perform lab debug and root-cause timing/functional issues using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram tools.

Requirements

Must-have technical skills and experience are listed below; bonus items are grouped separately.

• Proven experience taking FPGA designs from RTL through timing closure to validated hardware (ASIC prototyping/emulation or similar).
• Expert-level SystemVerilog and/or VHDL for synthesis; deep proficiency with Xilinx Vivado (synthesis, P&R, timing closure, IP).
• Hands-on experience implementing and debugging PCIe; familiarity with AXI/AHB, SPI, UART, JTAG, and common interfaces.
• Strong Python skills for automation, testing, and build tooling; C++ experience for hardware abstraction is desirable.
• Board-level bring-up and lab debugging skills on real hardware and experience with oscilloscopes, logic analyzers, and high-speed link characterization.
• Ability to work independently in a startup environment and handle ambiguous cross-disciplinary problems.

Nice-to-have / Bonus:

• Verification frameworks such as Cocotb or UVM.
• Experience deploying ML models to FPGAs (hls4ml, FINN) or building real-time, sub-microsecond signal-processing pipelines.
• Mixed-signal ASIC exposure (ADC/DAC interfaces, analog compute).
• SERDES tuning and signal integrity fundamentals.
• CI/CD for hardware (GitLab CI, Docker-based build/test).

Education Requirements

Not specified.

Normal Computing is an equal opportunity employer. Accessibility accommodations available; contact accommodations@normalcomputing.com for assistance.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.