Hardware Engineer (FPGA/ASIC) — Intern

Job Title

Hardware Engineer (FPGA/ASIC) — Intern

Role Summary

Summer internship on Jane Street's hardware engineering team. Interns are paired with full-time engineers and complete a focused project that uses the team's Hardcaml/OCaml toolchain to design, test, and validate FPGA or ASIC hardware.

Experience Level

Entry-level (Internship). Suitable for students or recent graduates; no specific years of professional experience required.

Responsibilities

Intern will work on a single mentored project and deliver a working hardware design. Typical responsibilities include:

• Design RTL and testbenches using Hardcaml and OCaml-based tooling.
• Implement and validate designs targeting FPGA or ASIC platforms.
• Use vendor toolchains (e.g., Vivado, Quartus, Genus, Innovus) for synthesis, place-and-route, and timing analysis.
• Build a working hardware project from concept through integration and testing.
• Collaborate with mentors and other engineers; incorporate feedback and iterate on designs.
• Focus work in the context of networking-related hardware tasks when relevant.

Requirements

Must-have skills and experience:

• Comfortable programming in at least one software language.
• Experience with a hardware description or construction language (VHDL, Verilog, Chisel, Pymtl, or similar) for both writing and testing designs.
• Experience using FPGA or ASIC vendor tools (e.g., Vivado, Quartus, Genus, Innovus).
• Experience building a working hardware project (academic, professional, or personal).
• Interest in applying FPGAs or ASICs in networking contexts.
• Fluent in English.

Education Requirements

Not specified.

About the Company

Company: Jane Street

Headquarters: London, United Kingdom

Jane Street is a global trading firm and liquidity provider that specializes in technology-driven strategies. Established in 2000, the company focuses on providing liquidity and improving market efficiency through advanced analytics and trading technologies.