Hardware Engineer, DFT

Job Title

Hardware Engineer, DFT

Role Summary

Owner of DFT architecture and implementation for next-generation ASICs, responsible for scan/ATPG, MBIST, boundary-scan, and test access infrastructure from RTL through tapeout and silicon bring-up.

Work closely with RTL, verification, physical design, and silicon product engineering teams to establish scalable DFT methodologies, tooling, and manufacturing test readiness.

Experience Level

Senior - requires 7+ years of hands-on DFT implementation experience for complex ASICs/SoCs, including successful tapeouts.

Responsibilities

Lead DFT architecture, integration, verification, and production test readiness across the silicon development lifecycle.

• Define chip-level DFT architecture: scan insertion, ATPG, scan compression, MBIST, boundary-scan/JTAG, and test access infrastructure.
• Drive DFT insertion and integration across RTL, synthesis, and physical design while minimizing impact on PPA.
• Perform ATPG pattern generation, fault coverage analysis, DFT verification, and signoff through tapeout.
• Deliver manufacturing test patterns, ATE integration documentation, silicon bring-up support, and failure diagnosis guidance.
• Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools.
• Manage and review work from external DFT implementation partners to ensure quality and integration.

Requirements

Must-have skills and experience for immediate effectiveness in the role.

• 7+ years of DFT implementation experience for complex ASICs/SoCs, including tapeouts.
• Hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
• Experience with MBIST, boundary scan/JTAG, and DFT integration at RTL and gate level.
• Proficiency with industry DFT tools (e.g., Siemens Tessent, Synopsys TestMAX, Cadence Modus).
• Solid understanding of RTL design, synthesis, static timing analysis, and physical design constraints.
• Experience delivering manufacturing test patterns and collaborating with ATE or silicon product engineering teams.
• Strong scripting skills (Python, Tcl, or similar) and ability to drive cross-functional technical decisions.

• Experience establishing DFT architecture and methodology for a new ASIC program.
• Familiarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression.
• Experience with memory redundancy, BISR, silicon diagnosis, and yield improvement.
• Exposure to AI accelerators, memory-intensive architectures, or unconventional computing systems.
• Experience using AI-assisted tools to automate silicon design and verification workflows.

Accessibility accommodations: Normal Computing provides reasonable accommodations. If you need assistance, contact accommodations@normalcomputing.com.

Education Requirements

Not specified.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.