Graduate Server CPU Physical Design Engineer

Job Title

Graduate Server CPU Physical Design Engineer

Role Summary

Join the Nuvia Data Centre CPU team in Cambridge to learn and contribute to the physical implementation of high-performance, power-efficient server CPU blocks. Work across RTL/netlist to GDS flows to meet performance, power, and area targets while collaborating with architecture, RTL, circuits, CAD, SoC integration, timing, power, and post-silicon teams.

Experience Level

Entry-level / Graduate — intended for recent graduates or early-career engineers; suitable for candidates with internship, project, or academic research experience. No specific years of experience required.

Responsibilities

Primary responsibilities include hands-on implementation tasks and collaborative engineering support across the CPU implementation flow.

• Contribute to CPU block physical implementation from RTL/netlist to GDS: synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, ECOs, and signoff.
• Support timing closure and implementation convergence across modes, corners, and operating conditions.
• Analyse and improve performance, power, and area (PPA) for high-performance, low-power CPU designs.
• Debug physical design issues related to timing, congestion, routing, clocking, power, physical verification (DRC/LVS), and ECO closure.
• Use industry-standard EDA tools for synthesis, place-and-route, static timing analysis, power analysis, and physical verification.
• Develop scripting and automation to improve productivity, data analysis, and design-flow efficiency.
• Collaborate with RTL, architecture, CAD, circuits, SoC, and post-silicon teams to understand design intent and trade-offs.
• Contribute to methodology improvements, automation, documentation, and data-driven analysis under senior guidance.

Requirements

Must-have technical skills and behaviours; preferred items listed as advantages.

• Solid understanding of digital logic design, CMOS fundamentals, and VLSI/semiconductor design concepts.
• Basic knowledge of static timing analysis concepts (setup, hold, clocking, timing paths, timing constraints).
• Scripting or programming experience in one or more of: TCL, Python, or Perl.
• Strong analytical and problem-solving skills with the ability to learn technical concepts quickly.
• Good communication skills and willingness to work in a collaborative, global engineering team.
• Familiarity with Linux-based engineering environments and EDA tool usage is advantageous.
• Exposure to Verilog/SystemVerilog, RTL concepts, CPU architecture, pipelines, caches, or low-power design is a plus.

Education Requirements

Bachelor’s, Master’s, or PhD in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, Microelectronics, Semiconductor Engineering, or a related technical field; or equivalent practical experience. Recent graduates with relevant internships, industrial placements, academic research, thesis or project work in VLSI/ASIC/CPU design are encouraged to apply.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.