GPU Validation and Emulation Engineer, Senior

Job Title

GPU Validation and Emulation Engineer, Senior

Role Summary

Work on GPU RTL validation and emulation to enable functional verification, system-level debugging, and post-silicon bring-up. The role sits on the GPU ASIC engineering team and collaborates with RTL designers, software/driver teams, and tool vendors.

Experience Level

Senior. Minimum qualifications indicate a degree plus experience: Bachelor's +2 years, Master's +1 year, or PhD (see Education Requirements for details).

Responsibilities

Primary responsibilities include implementing and validating RTL on emulator and FPGA platforms and driving system-level debug.

• Synthesize Verilog RTL and compile models to hardware emulators (Veloce/Palladium/ZeBu) and FPGA platforms.
• Develop emulator implementation: partitioning, synthesis, place-and-route, timing analysis, and run-time performance tuning.
• Drive debug of emulator failures; coordinate with designers and software/driver teams on test plans and root-cause analysis.
• Work with tool vendors to improve methodology for area and performance of synthesized FPGA RTL.
• Integrate third-party IP and perform system-level debugging.
• Perform system-level RTL simulation and design verification.
• Support chip bring-up and post-silicon debug; debug functional and timing models.

Requirements

Concise list of required and preferred technical skills. Education details are listed under Education Requirements.

• Must-have: Hands-on experience with RTL synthesis and mapping RTL to hardware emulators or FPGA-based emulation platforms.
• Must-have: Practical experience with hardware emulators or FPGA systems (examples: Palladium, ZeBu, Veloce, Xilinx/Altera-based FPGA flows).
• Must-have: Experience with synthesis/place-and-route, timing analysis, and performance optimization of synthesized RTL.
• Must-have: Debugging experience for emulator and post-silicon issues; familiarity with waveform viewers and system-level debug techniques.
• Must-have: RTL skills in Verilog/SystemVerilog and ability to support verification and timing model debug.
• Must-have: Programming/scripting skills (C/C++, Python, Tcl, or Perl) to automate flows and debug environments.
• Nice-to-have: UVM/SystemVerilog verification experience, knowledge of GPU/CPU/DDR/Bus subsystems, and familiarity with vendor emulation and synthesis tools.
• Nice-to-have: Experience creating high-performance, area-efficient emulation environments and hybrid emulation/simulation acceleration methodologies.

Education Requirements

Minimum qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field plus 2+ years of relevant engineering experience; OR Master's degree in those fields plus 1+ year of relevant experience; OR PhD in those fields. Preferred/Desirable mentions include MS degree and related technical degrees.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.