GPU Physical Design Engineer (Austin / San Diego)

Job Title

GPU Physical Design Engineer — Austin / San Diego

Role Summary

Senior individual contributor responsible for physical implementation of integrated graphics cores from RTL to GDS. Focus on complex, high-frequency blocks and top-level designs to meet aggressive power, performance, and area (PPA) targets.

Work closely with RTL/architecture teams, multidisciplinary engineering groups, and EDA/tool vendors to optimize designs and automate flow and methodology improvements.

Experience Level

Senior-level. The posting indicates very experienced candidates (the listing cites 17+ years of direct synthesis and physical design work). The Minimum Qualifications section also lists degree-based alternatives with lower experience thresholds (e.g., Bachelors +6 years, Masters +5 years, PhD +4 years).

Responsibilities

Deliver physical design solutions for high-performance GPU blocks and top-level chips while improving PPA and ensuring timing and reliability closure.

• Perform floor-planning, placement, clock implementation, and routing for complex, high-frequency designs.
• Drive physical synthesis and implementation using industry tools and techniques to meet PPA targets.
• Perform static timing analysis, power/PDN analysis, and reliability signoff.
• Collaborate with RTL designers and architects to identify and remove performance and power bottlenecks.
• Develop and improve automation, flows, and methodologies with internal teams and tool vendors.
• Lead block closure activities through tape-out, including DFT, timing, and reliability signoff.
• Debug complex issues, provide technical leadership, and coordinate cross-functional resolution.

Requirements

Must-have technical skills and proven experience in physical design and signoff for advanced, high-performance chips.

• Extensive hands-on physical design experience: floor-planning, placement, clocking, routing for complex designs.
• Proficiency with implementation and synthesis tools (examples: Synopsys Fusion Compiler, ICC2; Cadence Genus/Innovus).
• Strong knowledge of static timing analysis, power analysis, PDN, and signoff practices.
• Deep understanding of CMOS stdcell and memory circuits and techniques to optimize PPA.
• Practical experience with Synthesis, DFT, Place & Route, Timing and Reliability signoff flows.
• Ability to read and understand RTL (Verilog/SystemVerilog) and collaborate with RTL engineers.
• Scripting skills for automation (tcl, perl, or python).
• Excellent communication, debugging, and cross-team collaboration skills; demonstrated independent problem solving and technical leadership.

Nice-to-have:

• Experience with deep sub-micron process nodes (e.g., 4nm and below) and multiple tape-outs.
• Prior exposure to flow and methodology development and vendor collaboration for EDA tool enhancement.

Education Requirements

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field is cited. The posting also lists Master's and PhD as preferred/alternative qualifications. The Minimum Qualifications section states degree-plus-experience alternatives (e.g., Bachelor's +6 years; Master's +5 years; PhD +4 years). Equivalent practical experience is accepted where noted.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.