General RTL Engineer

Job Title

General RTL Engineer

Role Summary

Design and implement RTL for an SoC and processor in a small, early-stage startup team. You will own significant subsystems of the design and collaborate closely with Architecture, Verification, and Physical Design.

This role focuses on micro-architecture, pipelining, timing closure, and optimizing for power and area.

Experience Level

Mid-level. Specific years of experience not stated.

Responsibilities

Key responsibilities include:

• Develop RTL for processor and SoC blocks starting from micro-architecture to synthesizable implementation.
• Implement and optimize pipelining, timing closure, power and area trade-offs.
• Design and integrate IO, memory interfaces, and bus interfaces.
• Integrate third-party IP and develop glue logic.
• Collaborate with Architecture, Verification, and Physical Design to deliver tapeout-ready blocks.
• Own delivery of assigned design components and participate in design reviews.

Requirements

Must-have and preferred qualifications:

• Must-have: Strong background in RTL design and micro-architecture development, including experience with pipelining and timing closure.
• Must-have: Experience optimizing designs for power and area.
• Must-have: Experience working with cross-functional teams (architecture, verification, physical design).
• Nice-to-have: Experience with IOs, memory interfaces, and bus interfaces.
• Nice-to-have: Experience integrating third-party IP and developing glue logic.

Education Requirements

Not specified.

About the Company

Company: Akeana

Headquarters: Santa Clara, CA, USA

Akeana is a start-up specializing in processor design, with a team experienced in developing state-of-the-art products. Their expertise spans multiple architectures, including Risc-V, ARM, and x86, with backgrounds from prominent companies in the semiconductor industry. Funded by top-tier venture capitalists and industry leaders, Akeana focuses on innovative RTL design and micro-architecture development.