G7 Fellow – High-Speed Interfaces & Clocking Strategy
NXP SemiconductorsJob Title
G7 Fellow – High-Speed Interfaces & Clocking Strategy
Role Summary
Senior technical leader responsible for defining and driving company-wide strategy, roadmaps, and architectures for high-speed interfaces, clocking systems, and PLL technologies. The role aligns technology direction across business and product lines, advises on make-vs-buy decisions, and leads cross-functional engineering efforts to deliver scalable, low-jitter, low-power timing and connectivity solutions.
The position engages with internal product teams, external partners, standards bodies, and customers to ensure technical differentiation, platform reuse, and system-level clocking integrity across automotive, industrial, edge, networking, and compute products.
Experience Level
Senior-level (Fellow). Years of experience: Not specified.
Responsibilities
Lead technical strategy and architectural direction for high-speed interfaces and clocking across NXP products and business lines.
- Define long-term technology strategy and roadmaps for high-speed PHYs, SerDes, clocking architectures, and PLL technologies.
- Analyze requirements across product lines and recommend platform consolidation, reuse, and architectural alignment.
- Assess portfolio and make-versus-buy decisions for PHYs, SerDes, clocking, and related IP; evaluate external IP and partnership opportunities.
- Drive next-generation clock generation and PLL solutions focused on low jitter, low power, small area, scalability across process nodes, and functional safety.
- Develop architectural frameworks for clock distribution, synchronization, timing integrity, and system-level clock management.
- Provide technical leadership for connectivity technologies and future PHY/SerDes architectures to support multi-gigabit and chiplet systems.
- Lead benchmarking, technology assessments, and innovation roadmaps; represent the company with customers, partners, and standards organizations.
Requirements
Must-have skills and experience to perform the role; followed by notable nice-to-have qualifications.
- Proven senior technical leadership in high-speed interfaces, PHY/SerDes architectures, or clocking/PLL technologies.
- Deep technical knowledge of PLLs, clock generation, distribution, synchronization, and timing integrity (low jitter, low power, area, scalability).
- Experience defining technology roadmaps, architectural frameworks, and cross-product platform strategies.
- Track record making strategic make-vs-buy decisions and evaluating external IP and partner opportunities.
- Ability to lead cross-functional engineering teams and represent the company in technical discussions with customers, partners, and standards bodies.
- Strong analytical skills for benchmarking, technology assessment, and trade-off analysis.
- Nice-to-have: experience across automotive, industrial, secure edge, networking, and compute markets; familiarity with PCIe, CXL, UCIe, DDR, MIPI, Ethernet, USB/eUSB, I3C, and chiplet interconnects; functional-safety experience.
Education Requirements
Not specified.
About the Company
Company: NXP Semiconductors
Headquarters: Nijmegen, Netherlands
NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.
