Fundamental IP Design Kit and Characterization Manager
QualcommJob Title
Fundamental IP Design Kit and Characterization Manager
Role Summary
Lead development, characterization, and delivery of IP blocks (I/O, memory, standard cell libraries) and associated design-kits for advanced CMOS/FinFET nodes. Work with cross-functional global teams to define methodologies, automate flows, and support SoC integration for mobile, automotive, IoT, and consumer products.
Experience Level
Senior (Manager level). Typical guidance: 6+ years ASIC/IP design, verification, validation, integration, or related experience; alternative degree/experience combinations described in Education Requirements.
Responsibilities
Primary responsibilities include technical leadership, delivery of design-kits and models, and supporting SoC teams through integration and sign-off.
- Lead end-to-end development and delivery of IP blocks and SoC-level integrations, including documentation and verification plans.
- Create and validate behavioral and transistor-level models (Verilog/SystemVerilog, transistor simulations) for I/Os, memories, and standard cells.
- Develop and automate characterization and sign-off flows using scripting (Python, Perl, TCL) on UNIX/Linux.
- Maintain Liberty formats, statistical variation models, and design-kit views; support STA, physical design, and SPICE simulations.
- Drive methodology and flow improvements with internal teams and external EDA/tool vendors.
- Debug IP and SoC issues, mentor junior engineers, and produce technical documentation.
Requirements
Concise list of required skills and experience. Preferred items are listed separately.
Must-have:
- Standard cell, memory, and I/O circuit knowledge plus IP characterization and design-kit delivery experience.
- 6+ years of ASIC/IP design, verification, validation, integration, or related work experience (Manager level).
- Strong programming/scripting on UNIX/Linux (Python, Perl, or TCL) and experience automating characterization flows.
- Familiarity with Liberty formats (NLDM, CCS, LVF), statistical variation models, and multiple design-kit views.
- Experience with RTL design/coding, verification (including SVA), DFT/BIST modeling, and static timing analysis.
- Solid knowledge of CMOS/FinFET transistor fundamentals and digital circuit optimization.
- Excellent analytical, debugging, communication, and collaboration skills; experience supporting cross-functional SoC teams.
Nice-to-have / Preferred:
- Experience with analog/mixed-signal simulations and commercial characterization tools.
- Large-scale software automation, data analysis, and visualization experience for characterization/sign-off.
- Silicon reliability modeling and multi-foundry validation experience; exposure to advanced chip design tools and RTL-to-GDSII flows.
- Prior experience interacting with senior leadership and working in multi-site project teams with third-party vendors.
Education Requirements
Degrees accepted: Bachelor's, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Minimum experience alternatives stated by employer: Bachelor's +6 years, Master’s +5 years, or PhD +4 years of relevant ASIC/IP design, verification, validation, integration, or related experience. Equivalent practical experience in lieu of a degree is acknowledged by the employer.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
