Functional Verification Lead

Job Title

Functional Verification Lead

Role Summary

Technical lead for functional verification of high-speed memory controller IP and UCIe designs. The role owns verification strategy, environment development (simulation and formal), and delivery of verification closure for DDR5/6 RLD3 Memory Controller and related IPs.

Will lead and mentor a verification team in Hyderabad, coordinate with design teams, and ensure on-schedule verification delivery to programs.

Experience Level

Senior. Typical experience expected: PhD with 9+ years, MS with 11+ years, or BS with 12+ years in relevant engineering roles.

Responsibilities

Primary responsibilities include leading verification efforts, defining methodology, and delivering verified IP to schedule.

• Lead verification strategy and execution for high-performance memory controller IP and UCIe designs.
• Design, develop, and maintain simulation and formal verification environments at block and system levels.
• Develop and run UVM/SystemVerilog testbenches and use simulation/debug tools (e.g., Synopsys VCS, Cadence IES).
• Define verification closure criteria, track progress, and report status to program stakeholders.
• Mentor and manage a verification team (~9+ engineers), coordinate cross-functional work with design teams.
• Establish assertion- and metric-driven verification methodologies and act as a verification architect.
• Manage regression infrastructure and verification databases; oversee gate-level, power, reset, and contention checks.
• Support silicon bring-up and board/tester-level debug activities.

Requirements

Must-have technical skills and leadership experience; listed concisely below.

• Hands-on experience verifying memory controllers (HBM, DDR, LPDDR) and UCIe IP.
• Strong knowledge of memory controller protocols, calibration specifications, and board skew/jitter modeling.
• Practical experience with UVM/OVM and SystemVerilog/Verilog testbench development.
• Experience using simulation and debug environments such as Synopsys VCS and Cadence IES.
• Proven track record of technical leadership and delivery of verification for high-performance IP or SoC designs.
• Experience with assertion-based and metric-driven verification and regression management systems.
• Excellent communication and cross-team collaboration skills.

Nice-to-have:

• Experience with formal property checking tools (Cadence, Jasper, Synopsys formal tools).
• Experience with gate-level simulation, power verification, reset verification, and contention checking.
• Prior silicon debug at board and tester level.
• Background as a verification architect establishing methodology and tools for IP/VLSI designs.

Education Requirements

Bachelor's degree with 12+ years, Master's degree with 11+ years, or PhD with 9+ years in Electrical Engineering, Computer Engineering, or Computer Science.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.