Functional Safety Architect

Job Title

Functional Safety Architect

Role Summary

Owner of device-level functional safety architecture for next-generation semiconductor SoC devices. Lead development of technical safety concepts, allocate decomposed safety requirements to IP blocks, and coordinate with architecture, RTL, firmware, verification and physical design teams to achieve functional safety certification.

Experience Level

Senior-level. Typical experience: MS + ~8 years or BS + ~10 years of silicon industry experience (senior/lead responsibility expected).

Responsibilities

Deliver and maintain defensible safety architecture and evidence to achieve certification; collaborate across engineering teams to integrate safety mechanisms.

• Define device safety architecture and decompose safety requirements to IP/subsystems.
• Perform safety analyses (FTA, FMEA/FMEDA, HAZOP) and address common-cause failures, independence and fault tolerance.
• Specify safe-architecture patterns (lockstep CPUs, ECC memories, watchdogs, redundancy) and required diagnostics.
• Review and contribute to safety requirement specifications together with functional safety engineers.
• Guide ASIL/SIL decomposition, fault tolerance targets and diagnostic coverage strategies.
• Review hardware and software safety designs for compliance and implementation feasibility.
• Define safety verification & validation strategy (fault injection, fault simulation, test methods) with verification teams.
• Track and ensure achievement of diagnostic coverage metrics (SPFM, LFM, PMHF) and related KPIs.
• Document and present safety-case evidence aligned to standards for internal stakeholders and external assessors.

Requirements

Must-have technical skills and domain experience; preferred items listed separately.

• Proven experience in functional safety for silicon/ASIC/SoC devices and delivering safety artefacts through development.
• Skilled with safety-analysis methods and tooling: SysML, FMEA/FMEDA, FTA, HAZOP and requirements-management tools (e.g., Jama).
• Experience defining and reviewing diagnostics, fault-tolerance and hardware/software safety mechanisms.
• Ability to translate system-level safety goals into detailed, testable requirements and implementation constraints.
• Experience collaborating with architects, RTL teams, firmware, physical design and verification organizations.
• Strong written and verbal communication: prepare evidence-based safety arguments and communicate with assessors and customers.
• Preferred: familiarity with RTL coding, SoC simulation/debug, customer engagement on safety use-cases, and managing multi-year programs.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering (or equivalent). Typical experience expectation: BS + 10 years silicon industry experience or MS + 8 years. Relevant safety professional certifications and accreditation are expected (examples: FSCP or equivalent professional safety certifications) and experience certifying devices through organisations such as EXIDA or TÜV (or equivalent). "Or equivalent practical experience" is acceptable as stated in the source.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.