Fullchip Floorplan Design Engineer

Job Title

Fullchip Floorplan Design Engineer

Role Summary

Responsible for top-down SoC floorplanning and physical design decisions for complex system-on-chip products. The role collaborates with architects, block leads, clock and power teams, and package/platform engineers to define placement, power domains, bump planning, and die dimensions to meet area, latency, power, and schedule targets.

Works within a physical design team to drive floorplan execution, supervise block-level placement tradeoffs, and improve methodologies and automation for timely convergence.

Experience Level

Mid-level. The posting indicates experienced-hire candidates with multiple years of relevant physical design and floorplanning experience (tool and domain experience required).

Responsibilities

Key responsibilities focused on top-down floorplanning, coordination across domains, and delivery of physical design-ready layouts.

• Perform top-down SoC floorplan activities: optimal IP placement, partitioning, pin-cutting, bump and I/O planning in collaboration with architects and package/platform teams.
• Estimate die area and recommend physical dimensions, technology/metal-stack choices, and reuse strategies to optimize cost and manufacturability.
• Plan multi-power-domain layouts, create power grid strategies, and coordinate level shifters/isolation and thermal considerations.
• Drive and supervise smaller blocks/subsystems to influence placement, shape, and channel planning for area and convergence targets.
• Collaborate with clock design, power delivery, and APR teams to produce block-level floorplans suitable for place-and-route.
• Develop and improve floorplanning methodologies, tools, and automation to streamline physical design flow.
• Plan short- and long-term schedules and manage dependencies across top-level and block-level physical design activities.

Requirements

Minimum technical and tool experience required for initial consideration; preferred items are listed separately.

• 2+ years experience using industry-standard EDA tools for floorplanning and APR.
• Experience with multi-power-domain designs (1+ years on large designs noted in posting).
• Experience with Synopsys Fusion Compiler (1+ years) or similar place-and-route tools.
• Strong scripting/automation skills: TCL, Python, or Perl (3+ years experience indicated).
• Experience with physical verification tools such as Calibre or ICV (2+ years).

Nice-to-have:

• Knowledge of ASIC integration: clock and power distribution, global signal planning, I/O planning, and macro placement.
• Familiarity with hierarchical/top-down design, handling multiple-instantiation blocks, routing, and physical convergence flows.
• Experience with large subsystem designs (tens of millions of gates) and high-frequency designs.
• Familiarity with UPF/CPF and low-power static verification planning.
• Experience with ICC2/FC floorplanning tools and full place-and-route/physical verification flows.
• Strong communication and teamwork skills.

Education Requirements

Posting specifies a Bachelor's degree in Electrical, Electronics, or Computer Engineering (with 3+ years relevant experience) or a Master's degree in those fields (with 2+ years relevant experience). Experience can be obtained via degree, research, previous job, or internship; equivalent practical experience is implied where applicable.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.