Full Chip Timing Modeling and Integration Engineer

Job Title

Full Chip Timing Modeling and Integration Engineer

Role Summary

Join the Full Chip Timing team to develop timing methodologies and perform full-chip timing analysis for next-generation FPGA products. The role focuses on timing model generation, integration, validation, and collaboration with front-end and back-end design teams to ensure timing signoff.

Experience Level

Mid-level - typically requires 5+ years of relevant industry experience in SoC or semiconductor design and timing analysis.

Responsibilities

Execute full-chip timing flows, create and validate timing models, and resolve timing and extraction issues while coordinating with cross-functional teams.

• Develop timing methodologies and run full-chip timing analysis for advanced-process FPGA products.
• Define timing modeling strategies and produce high-level timing models.
• Integrate and validate timing models within the design flow.
• Create and maintain clocking schemes and timing constraints.
• Analyze extraction issues, design margins, and timing signoff requirements.
• Correlate STA results with SPICE and perform timing quality checks.
• Debug complex timing and implementation issues across multi-site teams.
• Drive continuous improvement of timing methodologies and automation.
• Communicate technical trade-offs and timing status to cross-functional stakeholders.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 5+ years industry experience in SoC development and working with advanced semiconductor process nodes.
• 5+ years experience with industry-standard timing formats and design constraints (Liberty, Verilog, Synopsys Design Constraints - SDC).
• 5+ years experience with Static Timing Analysis (STA), including correlating STA with SPICE.
• 5+ years experience in timing modeling and library quality assurance (QA).
• 5+ years experience scripting for design automation using Python and Tcl.
• 5+ years experience applying silicon modeling concepts such as LVF and POCV.
• Ability to work independently and within cross-functional, multi-site teams under aggressive schedules.
• Must be eligible for any required U.S. export authorizations.

Preferred:

• 7+ years of relevant industry experience.
• Experience with complex designs involving multiple voltage domains.
• Familiarity with functional and Design-for-Test (DFT) modes for timing constraint management.
• Background in FPGA architecture or interfaces such as DDR or PCIe.
• Experience applying AI/ML techniques to improve timing or automation flows.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as stated in Minimum Qualifications).

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.