Full Chip Timing / Constraints Lead

Role Summary

The role involves leading the Backend Full Chip Timing team within the Strategic Silicon Solutions Group Physical Design team at AMD. This position requires collaboration with various teams including PD architects, design leads, and engineers to ensure successful design execution and closure. The candidate will primarily focus on timing constraints development and achieving first-pass silicon success.

Experience Level

10+ years of experience in physical design, specifically in static timing analysis (STA), constraints, and timing signoff.

Responsibilities

• Lead the full chip timing team for constraints and timing signoff.
• Manage end-to-end delivery of designs from a timing perspective.
• Collaborate with SOC Architecture teams for clock and statistical timing goals.
• Set up design clock requirements accurately in SDC.
• Analyze timing margins on the latest technology nodes.
• Oversee the timing ECO phase and ensure timely project delivery.
• Work with CAD and EDA vendors to strengthen timing methodology.

Requirements

The ideal candidate should possess deep expertise in physical design tools, particularly SNPS PT/GCA and ICC2/FC. A strong understanding of Design for Test (DFT) concepts and scripting knowledge in Perl/TCL/Shell/Python is required. Good communication skills and attention to detail are essential attributes.

Education Requirements

Bachelor's or Master’s degree in Computer, Electronics, or Electrical Engineering.