Full-Chip Physical Design Verification Engineer
TenstorrentJob Title
Full-Chip Physical Design Verification Engineer
Role Summary
Lead full-chip physical verification and signoff for advanced-node SoCs to ensure manufacturable, high-quality silicon and successful tapeouts.
The role works across RTL, physical design, CAD, packaging, and foundry teams to drive closure of DRC/LVS/ERC/PERC and other PV checks, debug issues with industry PV tools, and implement flow automation.
Experience Level
Senior — typically 7–14 years of hands-on CPU/IP/SoC physical verification experience. Candidates will be assessed during interview to confirm seniority and compensation band.
Responsibilities
Primary responsibilities include full-chip signoff activities and cross-functional verification closure.
- Drive full-chip physical verification signoff (DRC, LVS, ERC, PERC, antenna checks, DFM) to tapeout.
- Debug and triage physical verification failures using industry tools and data (Calibre, ICV, Pegasus, etc.).
- Coordinate with RTL, PD, CAD, packaging, and foundry teams to resolve manufacturability and reliability issues.
- Develop and maintain PV flows, automation scripts, and regression suites to improve closure cycle time.
- Perform reliability analyses including IR drop and EM assessments and advise on fixes.
- Contribute to ESD planning, padring integration, bump/RDL strategies, and PDK-specific constraints.
- Mentor engineers and help establish scalable PV methodologies and best practices.
Requirements
Must-have technical skills and experience for immediate contribution.
- Strong practical experience with DRC, LVS, ERC, PERC, antenna, and DFM verification using industry-standard tools and flows (examples: Calibre, ICV, Pegasus, Foundry tools).
- Experience debugging complex PV failures and driving closure through multi-team collaboration.
- Knowledge of ESD planning, padring integration, and bump/RDL strategies; familiarity with reliability concerns (IR drop, EM).
- Hands-on scripting proficiency in Python and TCL for automation and flow optimization.
- Familiarity with advanced process nodes (7nm, 5nm, 3nm) and FinFET design considerations.
- Proven ability to lead signoff efforts and mentor junior engineers.
- Preferred: prior tapeout experience on CPU/IP/SoC projects and exposure to CAD/PD toolchains (Innovus, etc.).
Education Requirements
BS or MS in Electrical/Electronics Engineering or a related technical field (as stated). No other certifications or degree types were specified.
About the Company
Company: Tenstorrent
Headquarters: Austin, Texas, United States
Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.
