Front-End Implementation Engineer (Staff)

Job Title

Front-End Implementation Engineer (Staff)

Role Summary

Work on front-end implementation for large Snapdragon SoCs, responsible for timing constraints, physical synthesis, formal verification and functional ECOs to bridge RTL and physical design. Position sits on the Digital ASIC/Implementation team focused on core and chip-level implementation at advanced nodes (4nm and below).

Experience Level

Senior — role targets experienced engineers. The posting indicates roughly 5–10 years of relevant ASIC implementation experience; candidates with equivalent experience will be considered.

Responsibilities

Key responsibilities include implementation tasks across RTL-to-physical design flow:

• Develop and manage top-level timing constraint sets and timing closure activities for large SoCs.
• Create and maintain TCL-based constraint and Synopsys tool flows; implement functional and timing ECOs.
• Perform physical synthesis and handoff to place-and-route teams; resolve synthesis-related issues.
• Run and analyze static timing analysis (STA) to identify and fix timing violations.
• Apply formal verification techniques to validate design intent and ECO correctness.
• Implement DFT and support test insertion and signoff activities.
• Use scripting (TCL, Perl, Python) to automate CAD/implementation flows and checks.
• Work with RTL designers on Verilog changes required for implementation and ECOs.

Requirements

Must-have technical skills and experience:

• Proven experience with logical and physical synthesis and timing closure practices.
• Experience capturing timing constraints (TCL) for Synopsys tool flows and STA methodologies.
• Practical knowledge of formal verification and implementation of functional/timing ECOs.
• Experience with Verilog RTL and debugging RTL/implementation interactions.
• Experience with UPF, low-power verification checks, and static timing signoff practices.
• Familiarity with DFT concepts and implementation for testability.
• Ability to develop automation scripts for CAD flows using TCL, Perl or Python.

Nice-to-have:

• Prior experience on large, advanced-node SoC projects (4nm and below).

Education Requirements

Relevant degree preferred: Bachelor's or Master's in Electronics, Computer Engineering, Science, Engineering or related technical field. The posting also references PhD options. Minimum qualifications described: Bachelor's + ~4+ years, Master's + ~3+ years, or PhD + ~2+ years of ASIC design/verification/integration experience. Applications with equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.