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Front-End CAD Engineer

Etched
July 29, 2026
Full-time
On-site
Cupertino, California, United States
EDA Jobs, Level - Mid-Career

Job Title

Front-End CAD Engineer

Role Summary

Responsible for owning and operating the front-end CAD environment for ASIC/AI chip development. The role maintains build flows, tool configurations, and verification toolchains used by RTL and verification engineers.

Works closely with EDA vendors and internal teams to evaluate, deploy, automate, and sustain front-end tools and dashboards in a fully in-person engineering team based in Cupertino.

Experience Level

Mid-level (no explicit years of experience specified).

Responsibilities

Primary responsibilities include maintaining front-end flows, deploying verification tools, and enabling internal teams to run verification tasks efficiently.

  • Own and manage front-end CAD environment, including build flows, tool-specific flows, and tool installation/configuration.
  • Evaluate, deploy, and sustain front-end tools: RTL simulators, low-power checkers, static RTL checkers (lint, CDC/RDC), SDC/DFT, and formal verification tools.
  • Configure and maintain project execution and verification dashboards.
  • Automate and optimize CAD workflows for chip design verification.
  • Interface with EDA vendors and internal users to identify needs, prioritize capabilities, and drive tool adoption.

Requirements

Looking for hands-on CAD engineers experienced with front-end flows and verification tooling.

  • Must-have: Experience developing and maintaining front-end IC design flows, including scripting and EDA tool configuration.
  • Must-have: Proficiency with verification tools such as RTL simulation, static checks (lint, CDC/RDC), formal tools, and low-power tools.
  • Must-have: Ability to automate CAD workflows and deliver deployable solutions.
  • Must-have: Ability to work directly with EDA vendors and internal engineering teams to identify and implement required capabilities.
  • Nice-to-have: Hands-on RTL design experience and ownership of a design block to validate CAD methodologies.
  • Nice-to-have: Experience working with Synopsys or Cadence teams or at other chip companies (e.g., Nvidia, Intel, AMD, Qualcomm, Marvell, Broadcom).

Education Requirements

Not specified.


About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.

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Date Posted: 2026-07-22