Front-End ASIC Engineer

Job Title

Front-End ASIC Engineer

Role Summary

Design and deliver digital IP for Power Management ICs (PMICs), focusing on RTL implementation, synthesis, verification, and tapeout signoff. Work on a cross-functional hardware team with Analog Design, Architecture, DFT, ATE, verification, and Silicon Validation to meet power, performance, area, and schedule targets.

Hands-on role covering SystemVerilog RTL, low-power techniques, PPA analysis, and supporting silicon bring-up.

Experience Level

Mid-level. The posting does not specify years of experience but expects demonstrated ASIC front-end design and signoff experience.

Responsibilities

Primary responsibilities include:

• Develop RTL in SystemVerilog for digital control logic and finite-state machines for PMIC digital IP.
• Synthesize RTL into gates and analyze power, performance, and area using tools such as Synopsys Design Compiler, Cadence Genus, and PrimeTime PX.
• Perform RTL simulation and functional verification using Cadence Xcelium, SimVision, or Synopsys simulators; collaborate with verification teams.
• Apply low-power design techniques, including clock and power gating.
• Perform CDC and RDC analysis and verification; maintain and cleanup SDC and other constraint files.
• Execute tapeout signoff duties, review STA reports, and confirm design meets timing, power, and area targets.
• Generate power reports across scenarios and corners; identify dynamic and leakage power contributors and recommend RTL/architectural improvements.
• Support Silicon Validation by explaining design functionality, reviewing test plans, and assisting with debugging.
• Use scripting (Perl, Python) to support ASIC flow development and automation.
• Coordinate with program managers to track project progress and deliverables.

Requirements

Must-have skills and tools:

• Proven experience designing digital logic in ASIC using SystemVerilog.
• Simulation with Cadence or Synopsys SystemVerilog simulators (e.g., Xcelium).
• Waveform analysis and debugging using Cadence Indago or SimVision.
• Synthesis experience with Synopsys Design Compiler or Cadence Genus.
• Experience with CDC and RDC verification tools.
• RTL and gate-level power estimation and analysis using Synopsys PrimeTime.
• Tapeout signoff experience, including reviewing STA reports and constraint files.
• Ability to author design specifications and collaborate across multiple engineering disciplines.

Education Requirements

Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.

About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.