Frame Engineering Intern (Jan–Jun 2027)

Job Title

Frame Engineering Intern (Jan–Jun 2027)

Role Summary

Work in the Tape-out organization supporting frame design, tape-out operations, and process improvements for semiconductor production at the Singapore Woodlands site. The role involves collaborating with global teams, using design and automation tools, and applying structured problem solving to reduce risks and improve cycle time.

Experience Level

Entry-level internship for students currently enrolled in a university degree program; suitable for candidates with limited professional experience.

Responsibilities

Typical tasks and project work during the internship may include:

• Design and generate frame structures/layouts for a range of technologies and manage frame-related change execution.
• Use or customize internal and commercial software tools to automate design inputs for fabs and mask houses.
• Prioritize work queues, coordinate hand-offs across geographic locations, and escalate tape-out issues as needed.
• Collaborate with Application Engineering, Product Engineering, Release Team, Design Enablement, FAB and TD teams to resolve tape-out and manufacturing issues.
• Participate in continuous improvement, document processes, perform Failure Mode and Effects Analysis, and propose automation opportunities.
• Support safety, environmental, health and security requirements in daily activities.
• Deliver a capstone presentation summarizing project results, learnings and recommendations.

Requirements

Must-have technical skills, availability, and internship conditions:

• Working knowledge of Unix shells and willingness to learn domain-specific scripting/programming and data formats.
• Experience with Cadence Virtuoso environment and SKILL programming.
• Ability to work at least 40 hours per week for the duration of the internship.
• Available for a 16–24 week credit-bearing internship commencing January 2027.

Nice-to-have:

• Prior internship or co-op experience in semiconductor or related industries.
• Device layout knowledge or experience.
• Experience with Cadence Mask Compose.
• Inquisitive mindset and proactive learning attitude.

Education Requirements

Actively pursuing a Bachelor's degree (undergraduate) in Chemical Engineering, Electrical/Electronic Engineering, Mechanical Engineering, Physics, or a related technical field from an accredited program. Must be in good academic standing and eligible for a 16–24 week credit-bearing internship beginning January 2027.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.