Frame Engineering Intern (Jan–Jun 2027)

Job Title

Frame Engineering Intern (Jan–Jun 2027)

Role Summary

Intern within the Tape-out organization supporting frame engineering and tape-out operations in Singapore. The role focuses on frame design, generation, and process improvements to increase productivity and quality for semiconductor manufacturing.

The intern will work with global Frame engineers, fabrication (FAB) teams, test and metrology engineers, and design enablement to apply structured problem solving and risk-reduction actions.

Experience Level

Entry-level internship for current undergraduate students. Suitable for those with limited professional experience; requires availability to start January 2027 for a 16–24 week credit-bearing placement and ability to work at least 40 hours per week.

Responsibilities

Core operational and project tasks the intern will perform:

• Support daily tape-out operations: define technology frame requirements, create frame structures/layouts, generate frames, execute ad-hoc changes, prioritize work queues, and perform hand-offs across locations.
• Use or customize internal and commercial software to automate and improve design workflows; generate input files for Fabs and Mask Houses.
• Assess and escalate tape-out support issues; recommend hold/promote/reject actions in coordination with FAB, Tape-out Logistics, and FAEs.
• Collaborate with Application Engineering, Product Engineering, Release, and Design Enablement teams to improve customer tape-out experience.
• Work with FAB and Technology Development teams to identify efficiency, cost, and cycle-time improvements.
• Participate in process reviews, perform Failure Mode and Effects Analysis (FMEA), document failure modes and mitigations, and propose automation opportunities.
• Follow Environmental, Health, Safety & Security requirements and promote safe work practices.
• Deliver a capstone presentation summarizing project results, learnings, and recommendations.

Requirements

Summary of required and preferred skills. Education degree requirements are listed under Education Requirements below.

Must-have

• Working knowledge of Unix shells and willingness to learn domain-specific scripting/programming and data formats.
• Ability to work at least 40 hours per week during the internship and commit to a 16–24 week, credit-bearing placement starting January 2027.
• Interest in semiconductor manufacturing processes and structured problem solving.

Nice-to-have

• Experience with Cadence Mask Compose.
• Experience with Cadence Virtuoso environment and SKILL programming.
• Device layout knowledge or prior exposure to layout tools.
• Prior internship or co-op experience, leadership in projects or competitions, and project management skills.
• Interest in using AI tools and emerging technologies to improve productivity and workflows.

Education Requirements

Actively pursuing a Bachelor's degree (undergraduate) in Chemical Engineering, Electrical/Electronic Engineering, Mechanical Engineering, Physics, or a related technical field through an accredited program. Must be in good academic standing. This is a credit-bearing internship scheduled to start January 2027 for 16–24 weeks.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.