Frame Engineering Intern (Jan-Jun 2027)

Job Title

Frame Engineering Intern (Jan–Jun 2027)

Role Summary

Internship position within the Tape-out organization supporting frame design, frame generation, and tape-out operations for GF's Singapore facility. The role involves using and customizing automation tools, coordinating across global teams, and driving process improvements to increase productivity and quality.

This is a project-focused, mentored internship with hands-on exposure to wafer fabrication tools and cross-functional collaboration with FAB, Application Engineering, Product Engineering, Release, and Design Enablement teams.

Experience Level

Entry-level internship for current undergraduate students. Suited for candidates with limited industry experience; practical coursework or prior internships are a plus. Internship duration: 16–24 weeks starting January 2027.

Responsibilities

Typical responsibilities and project work include:

• Support daily tape-out operations: manage technology frame requirements, frame layout and generation, change execution, work queue prioritization, and cross-site hand-offs.
• Use or customize internal and commercial software to automate design inputs for fabs and mask houses.
• Assess and escalate tape-out issues; make hold/promote/reject decisions in alignment with FAB and Tape-out Logistics.
• Collaborate with Application Engineering, Product Engineering, Release, Design Enablement, FAB and TD teams to resolve issues and improve cycle time and cost.
• Document processes, perform Failure Mode and Effect Analysis, and implement mitigation and detection controls.
• Identify and propose continuous improvement and automation opportunities to increase team productivity.
• Perform work safely and follow Environmental, Health, Safety & Security requirements.

Requirements

Key requirements and competencies for the internship.

Must-have:

• Working knowledge of Unix shells and willingness to learn domain-specific scripting and data formats.
• Experience with Cadence Virtuoso environment and SKILL programming.
• Ability to work at least 40 hours per week during the internship and be available for a 16–24 week credit-bearing placement commencing January 2027.
• Good communication and ability to coordinate across teams and time zones.

Preferred / Nice-to-have:

• Prior related internship or co-op experience in semiconductor operations or design support.
• Device layout knowledge or experience.
• Experience with Cadence Mask Compose or similar mask/data composition tools.
• Inquisitive mindset and proactive learning attitude.

Education Requirements

Actively pursuing a Bachelor's degree (undergraduate) in Chemical Engineering, Electrical/Electronic Engineering, Mechanical Engineering, Physics, or a related technical field through an accredited program. Must be in good academic standing. Internship must be a credit-bearing 16–24 week placement starting January 2027.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.