FPGA Verification Engineer Level 5 - Linthicum

Job Title

FPGA Verification Engineer Level 5 - Linthicum

Role Summary

Lead verification efforts for FPGA-based digital subsystems used in space systems. You will design and scale a VUnit-based verification methodology, drive CI automation, and provide technical leadership across multiple programs while working from the Linthicum, MD campus.

This is a hands-on, team-leading engineering role focused on delivering coverage-driven verification and ensuring designs meet requirements for high-reliability aerospace applications.

Experience Level

Senior — expects experienced engineers; typical hires have 7–12+ years of relevant verification or FPGA/ASIC experience depending on degree (see Education Requirements).

Responsibilities

Primary responsibilities include defining and executing verification strategy, building reusable verification infrastructure, and leading personnel across programs.

• Create verification plans from system requirements, including scope, methodology, coding standards, coverage goals, and traceability.
• Design and deploy a reusable VUnit-based verification environment, libraries, VIP, and modular testbench architectures.
• Develop VHDL/SystemVerilog testbenches, VUnit test suites, functional coverage models, assertions, and directed/random stimulus.
• Implement CI/CD for nightly regressions, coverage collection, and metric reporting (example: Jenkins integrations).
• Automate test generation, execution, and result analysis using scripting (Python, Tcl, Makefile as needed).
• Perform root-cause analysis of simulation failures; coordinate hardware bring-up and lab validation to isolate and resolve issues.
• Deliver verification closure artifacts: functional/code-coverage reports and requirements-traceability demonstrating exit criteria.
• Lead, mentor, and coach early-career verification engineers; promote design-for-verification practices.
• Collaborate with design, systems, firmware, and software teams; participate in SRR/PDR/CDR/TRR reviews.
• Identify technical risks, define mitigations, and enforce compliance with internal processes and security standards.

Requirements

Must-have technical skills, security and workplace requirements.

• Proficiency in hardware description languages: VHDL, SystemVerilog, Verilog.
• Hands-on experience with VUnit and experience developing verification IP and testbenches.
• Experience with digital subsystem, FPGA and/or ASIC development and RTL debug.
• Familiarity with industry EDA tools (examples: Synopsys, Mentor Graphics).
• Experience creating verification plans, functional-coverage models, and performing coverage-driven verification through closure.
• Strong scripting ability for automation (Python, Tcl, Makefile) and experience integrating verification into CI pipelines.
• Proven communication, interpersonal, and presentation skills; experience mentoring junior engineers.
• U.S. Citizenship required; ability to obtain and maintain Top Secret/TS-SCI clearance with SAP access (no clearance required to start).
• Willingness to travel up to approximately 10% of the time.
• Ability to produce clear verification documentation and test evidence for reviews and audits.

Education Requirements

Degree and experience combinations expected: Bachelor's degree with 12 years of relevant experience, Master’s degree with 10 years, or PhD with 7 years in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.

About the Company

Company: Northrop Grumman

Headquarters: Falls Church, Virginia, United States

Northrop Grumman is a leading global aerospace and defense technology company that provides innovative solutions in mission systems, electronics, and software. With a legacy of significant advancements in technology, we empower employees to tackle complex challenges and create revolutionary systems that enhance global security. Our diverse teams focus on engineering innovation and product development, delivering solutions that support military and civilian customers worldwide.