FPGA IP Software Development Engineer

Job Title

FPGA IP Software Development Engineer

Role Summary

Responsible for designing, implementing, packaging, verifying, and releasing parameterizable FPGA Soft IP cores for Quartus and Platform Designer. Work spans RTL micro-architecture through customer-ready delivery, including documentation and hardware validation.

Experience Level

Senior. The posting specifies Bachelor's + 6 years, or Master's + 4 years, of FPGA/ASIC RTL or Soft IP design experience.

Responsibilities

Primary responsibilities include delivering production-quality Soft IP and supporting its lifecycle:

• Architect and implement Soft IP in Verilog, SystemVerilog, or VHDL focusing on performance, resource usage, and timing closure.
• Develop parameterizable, reusable IP with clear configuration and stable upgrade behavior across Quartus releases.
• Own RTL design activities: synthesis, functional simulation, lint, CDC analysis, and static timing analysis (STA).
• Package IP for Quartus / Platform Designer (Qsys) including metadata, HDL generation, and parameter validation.
• Define register maps and control interfaces (CSR/AXI-Lite or Avalon-MM) and user data interfaces (AXI-Stream, Avalon-ST, or equivalent).
• Create and maintain simulation testbenches, directed and constrained-random tests, assertions, and regression suites to prove protocol compliance.
• Collaborate with verification, firmware, software, and hardware teams; support hardware bring-up on FPGA kits.
• Debug across simulation, synthesis, place-and-route, and hardware; perform root-cause analysis and deliver fixes.
• Author and review specifications, user guides, release notes, and API/register documentation.
• Lead technical reviews, enforce coding and quality standards, mentor junior designers, and support customer-facing inquiries.

Requirements

Must-have technical skills and experience for day-one effectiveness. See Education Requirements for degree and explicit years guidance.

• Proficiency in parameterizable RTL using Verilog, SystemVerilog, and/or VHDL.
• Experience taking IP through synthesis, simulation, timing constraints (SDC), CDC, and STA.
• Working knowledge of FPGA architecture, fabric resources, clocking, and Quartus or equivalent vendor design flows.
• Experience packaging or integrating IP in Platform Designer / Qsys, Vivado IP Integrator, or similar IP catalog flows.
• Familiarity with on-chip interconnect and control protocols (AXI4/AXI-Stream, Avalon-MM/Avalon-ST, CSR/register interfaces).
• Scripting for IP generation, regression, and automation (Python, Tcl, and/or Perl).
• Version control (Git) and structured code review experience.
• Strong debug, problem-solving, and written/verbal communication skills; able to work independently and lead technical discussions across sites.
• Ability to produce customer-ready documentation and example designs; support FAEs and design-in issues.

Education Requirements

Minimum: Bachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or a related field. Experience requirement tied to degree: Bachelor’s + 6 years, or Master’s + 4 years of FPGA/ASIC RTL or Soft IP design experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.