FPGA Engineer (VHDL) - Medical Devices

Job Title

FPGA Engineer (VHDL) - Medical Devices

Role Summary

The FPGA Engineer will design, implement, verify, and bring up FPGA-based systems for medical diagnostic and acquisition equipment. The role sits on an Agile engineering team responsible for FPGA RTL, high-speed I/O, data acquisition pipelines, and system integration.

Work includes architecture definition, development of reusable VHDL IP, timing closure, system-level verification, and supporting regulatory and quality documentation for medical devices.

Experience Level

Mid-level — approximately 4–10 years of hands-on FPGA design experience with VHDL (primary HDL).

Responsibilities

Own FPGA RTL design and verification for medical imaging and acquisition subsystems. Key responsibilities include:

• Architect and implement FPGA designs using VHDL; develop reusable IP (state machines, controllers, DSP modules, memory interfaces).
• Implement deterministic, low-latency data paths for diagnostic imaging and acquisition systems.
• Design and validate high-speed interfaces and front-end data paths (JESD204B/C, LVDS, MIPI, SPI, I2C, UART).
• Build high-throughput acquisition and buffering pipelines using DDR4/DDR5 and AXI interconnects.
• Ensure correct clocking, synchronization, CDC handling, and timing across reset and clock domains.
• Develop self-checking VHDL testbenches and perform block/system-level simulation and verification.
• Perform synthesis, place-and-route, timing analysis, and timing closure using Vivado or Quartus toolflows.
• Debug hardware and firmware issues using ILA/SignalTap, oscilloscopes, logic analyzers, and protocol analyzers; support lab bring-up.
• Contribute to documentation, requirements traceability, risk management, and verification artifacts required for medical device compliance.

Requirements

Must-have technical skills and experience:

• 4–10 years hands-on FPGA design experience with VHDL as the primary HDL.
• Strong understanding of synchronous digital design, clocking, CDC/reset-domain considerations, timing analysis, and timing closure.
• Experience with FPGA development on Xilinx/AMD or Intel platforms (Vivado preferred or Quartus).
• Proven ability to implement complex state machines, DSP blocks, memory interfaces, and high-throughput data paths.
• Familiarity with lab bring-up and system-level FPGA debugging using ILA/SignalTap and external measurement tools.
• Experience writing self-checking VHDL testbenches and using simulators such as ModelSim/QuestaSim, Vivado Simulator, or Riviera PRO.

Nice-to-have:

• Experience with JESD204B/C, DDR4/DDR5, AXI protocols, and precision ADC/DAC front ends.
• Familiarity with medical device regulatory standards, risk management, and verification processes (ISO 14971, IEC 62304, IEC 60601 family).

Education Requirements

Not specified.

About the Company

Company: EndoSec

Headquarters: Madison, WI, USA

Developer of hardware security solutions specializing in FPGA-based IP cores, cryptographic implementations, and embedded system integration for secure hardware and verification applications.