FPGA Engineer - Medical Devices (VHDL)

Job Title

FPGA Engineer - Medical Devices (VHDL)

Role Summary

The FPGA Engineer will design and verify FPGA-based systems for medical diagnostic and acquisition products. The role sits on an Agile engineering team responsible for RTL development, system bring-up, and delivering deterministic, low-latency data paths for imaging and sensing subsystems.

Work includes RTL architecture, IP development in VHDL, hardware bring-up and debugging, and supporting verification and regulatory documentation for medical devices.

Experience Level

Mid-level (4–10 years of relevant FPGA design experience, VHDL as primary HDL).

Responsibilities

Primary responsibilities include:

• Own FPGA RTL design using VHDL; develop reusable IP (state machines, controllers, DSP modules, memory interfaces).
• Implement deterministic, low-latency data paths for diagnostic imaging and acquisition systems.
• Translate system requirements into FPGA architecture with traceability to requirements.
• Implement and validate high-speed front-end interfaces (JESD204B/C, LVDS, MIPI) and serial/peripheral protocols (SPI, I2C, UART).
• Build high-throughput acquisition and buffering pipelines using DDR4/DDR5 and AXI interconnects.
• Ensure deterministic timing, synchronization, and clocking across modalities (ultrasound, CT, MRI, sensing subsystems).
• Develop self-checking VHDL testbenches and perform block/system-level simulation, synthesis, place & route, and timing closure.
• Perform linting and CDC/RDC checks; optimize power and resource utilization.
• Debug hardware and firmware using ILA/SignalTap, oscilloscopes, logic analyzers, and protocol analyzers; support lab bring-up.

Requirements

Must-have:

• 4–10 years hands-on FPGA design experience with VHDL as the primary HDL.
• Strong knowledge of synchronous digital design fundamentals, clocking, CDC and reset-domain considerations.
• Experience with timing analysis and timing closure workflows.
• FPGA development experience on Xilinx/AMD or Intel platforms (synthesis, P&R, timing tools).
• Proven ability to develop complex state machines, DSP blocks, and interface logic in VHDL.
• Familiarity with lab bring-up and FPGA system debugging (ILA/SignalTap, scopes, analyzers).
• Experience with simulation and verification tools such as ModelSim/QuestaSim, Vivado Simulator, or Riviera-PRO.

Nice-to-have:

• Experience implementing JESD204B/C and other high-speed ADC/DAC interfaces.
• Experience with DDR4/DDR5 memory interfaces and AXI-based data paths.
• Familiarity with medical device processes and standards (FDA design controls, EU MDR, IEC 62304, ISO 14971, IEC 60601) and requirements traceability tools.

Education Requirements

Not specified.

About the Company

Company: A&W Engineering Works

Headquarters: Sunnyvale, CA, USA

A&W Engineering Works develops and deploys end-to-end engineering solutions from front-end sensors to back-end applications, covering analog and digital signal processing, algorithms, hardware, software, mechanical design, rapid prototyping, and paths to production for complex real-world problems.