FPGA Engineer - Chip Design

Job Title

FPGA Engineer - Chip Design

Role Summary

Experienced ASIC/FPGA design engineer responsible for RTL development, verification, synthesis, implementation, and timing closure. The role focuses on creating realistic chip-design evaluation tasks and reference solutions used to assess AI-generated designs and agent performance.

Work with engineering and research teams to run EDA-based evaluation environments, identify functional and PPA issues, and improve automated test flows and benchmarks.

Experience Level

Mid-level - 3+ years of hands-on ASIC or FPGA design experience (typical range 3–5 years).

Responsibilities

Primary duties combine chip-design engineering and the construction of technical evaluations for AI systems.

• Design realistic evaluation tasks spanning RTL, verification, synthesis, physical design, and sign-off.
• Implement reference designs in Verilog/SystemVerilog or VHDL with testbenches, constraints, and expected results.
• Define grading criteria and validation methods aligned with industry engineering expectations.
• Review AI-generated RTL, testbenches, implementation results; identify functional errors and design weaknesses.
• Diagnose verification failures, coverage gaps, timing violations, and suboptimal PPA decisions.
• Evaluate designs for functional correctness, timing, resource usage, and implementation quality.
• Configure and maintain EDA environments to allow AI agents to execute realistic chip-design flows.
• Develop tasks that assess synthesis quality, place-and-route results, static timing analysis, and timing closure.
• Automate design flows, testing, and result analysis using scripting where appropriate.
• Document reference solutions, assumptions, failure cases, and evaluation methodologies.

Requirements

Must-have technical skills and practical experience for immediate contribution.

• 3+ years of hands-on ASIC or FPGA design experience across multiple stages of the digital flow.
• Strong RTL development skills in Verilog, SystemVerilog, or VHDL.
• Practical experience with design verification, including testbench development, debugging, coverage analysis, and UVM or similar methodologies.
• Working knowledge of EDA tools and workflows (Synopsys, Cadence, Siemens, AMD/Xilinx, Intel) and design implementation flows.
• Solid understanding of logic synthesis, place-and-route, static timing analysis, timing constraints, and timing closure.
• Experience taking at least one project from specification through implementation or tape-out.
• Strong debugging, analytical, and problem-solving skills; able to explain why a design succeeds or fails.

Nice-to-have:

• Familiarity with Python, Tcl, or Perl for automation.
• Exposure to open-source flows/tools (Yosys, OpenROAD, Verilator, cocotb).
• Interest or experience in AI-driven evaluations, reinforcement-learning environments, or model post-training.

Education Requirements

B.E./B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline.

About the Company

Company: Weekday

Weekday is a startup (YC W21) that connects companies with engineering talent and builds evaluation platforms; in this context it provides AI-assisted technical assessments and hiring services for chip design and semiconductor roles.