FPGA Engineer

Job Title

FPGA Engineer

Role Summary

Develop FPGA firmware and IP for medical imaging and data-acquisition systems as part of an Agile development team. Implement VHDL RTL, integrate high-speed interfaces and buffering, and produce designs that meet system requirements and regulatory documentation needs.

Experience Level

Mid-level. Source indicates 4–10 years of hands-on FPGA design experience with VHDL as the primary HDL.

Responsibilities

Primary ownership of FPGA architecture, RTL development, verification, and system bring-up for medical devices.

• Own FPGA RTL design using VHDL; develop reusable IP (state machines, controllers, DSP modules, memory interfaces).
• Implement deterministic, low-latency data paths for diagnostic imaging and acquisition systems.
• Translate system requirements into FPGA architecture with traceability to requirements.
• Design and validate high-speed I/O and precision ADC/DAC interfaces (JESD204B/C, LVDS, MIPI, SPI, I²C, UART).
• Build high-throughput acquisition and buffering pipelines using DDR4/DDR5 and AXI interfaces.
• Ensure deterministic timing, synchronization, and clocking across modalities (ultrasound, CT, MRI, sensing subsystems).
• Develop self-checking VHDL testbenches and perform simulation, synthesis, place-and-route, and timing closure.
• Debug hardware and FPGA logic using ILA/SignalTap, oscilloscopes, logic and protocol analyzers.
• Support compliance documentation, risk management, and verification per relevant medical-device standards.

Requirements

Key must-have skills followed by desirable skills relevant to the role.

• Must-have: 4–10 years hands-on FPGA design experience with VHDL as the primary HDL.
• Must-have: Strong synchronous digital design fundamentals: clocking, CDC/reset-domain considerations, timing analysis and closure.
• Must-have: FPGA development experience on Xilinx/AMD or Intel platforms, including synthesis and P&R flows.
• Must-have: Proven ability to develop complex state machines, DSP blocks, and interface logic in VHDL; familiarity with lab bring-up and system debugging.
• Must-have: Experience with simulation and verification tools such as ModelSim/QuestaSim, Vivado Simulator, or Riviera PRO; ability to create self-checking testbenches.
• Nice-to-have: Experience with JESD204B/C, LVDS, MIPI, high-speed ADC/DAC front ends, DDR4/DDR5 and AXI-based data pipelines.
• Nice-to-have: Familiarity with medical-device standards and regulatory processes (FDA, EU MDR, IEC 62304, ISO 14971, IEC 60601) and risk/hazard analysis practices.

Education Requirements

Not specified.

About the Company

Company: EndoSec

Headquarters: Madison, WI, USA

Developer of hardware security solutions specializing in FPGA-based IP cores, cryptographic implementations, and embedded system integration for secure hardware and verification applications.