FPGA Engineer

Job Title

FPGA Engineer

Role Summary

Join an Agile hardware engineering team developing FPGA-based systems for medical imaging and data acquisition. You will own RTL design and implementation for deterministic, low-latency signal paths and interfaces, and support verification, timing closure, and system bring-up.

Experience Level

Mid-level — typically 4–10 years of hands-on FPGA design experience (VHDL primary).

Responsibilities

Primary responsibilities include FPGA architecture, RTL development, verification, and system-level debugging for medical device applications.

• Own FPGA RTL design using VHDL; develop reusable IP (state machines, controllers, DSP modules, memory interfaces).
• Implement deterministic, low-latency data paths for diagnostic imaging and acquisition systems.
• Translate system requirements into FPGA architecture with traceability.
• Implement and validate high-speed I/O and precision ADC/DAC interfaces (JESD204B/C, LVDS, MIPI, SPI, I2C, UART).
• Design high-throughput acquisition and buffering pipelines using DDR4/DDR5 and AXI.
• Perform simulation, synthesis, place & route, timing analysis, linting, CDC checks, and timing closure.
• Debug hardware and programmable logic using ILA/SignalTap, oscilloscopes, and protocol analyzers.
• Support documentation, requirements traceability, risk management, and verification activities required for medical device compliance.

Requirements

Must-have technical skills and experience for immediate contribution.

• 4–10 years hands-on FPGA design experience with VHDL as the primary HDL.
• Strong knowledge of synchronous digital design fundamentals, clocking, CDC/reset-domain considerations, and timing analysis/closure.
• Experience with FPGA toolflows and platforms (Xilinx/AMD preferred or Intel/Altera).
• Proven ability to develop complex state machines, DSP blocks, and interface logic in VHDL.
• Experience with high-speed interfaces and data acquisition (JESD204B/C, LVDS, MIPI, SPI, I2C, UART) and memory interfaces (DDR4/DDR5, AXI).
• Experience creating self-checking testbenches and using ModelSim/QuestaSim, Vivado Simulator, or Riviera PRO for simulation.
• Familiarity with lab bring-up and FPGA system debugging tools (ILA/SignalTap, oscilloscopes, logic/protocol analyzers).
• Understanding of power/resource optimization, CDC/RDC checks, and timing closure processes.

Education Requirements

Not specified.

About the Company

Company: A&W Engineering Works

Headquarters: Sunnyvale, CA, USA

A&W Engineering Works develops and deploys end-to-end engineering solutions from front-end sensors to back-end applications, covering analog and digital signal processing, algorithms, hardware, software, mechanical design, rapid prototyping, and paths to production for complex real-world problems.