FPGA Engineer
CerebrasJob Title
FPGA Engineer
Role Summary
The FPGA Engineer will design and deliver the in-chassis IO subsystem for Cerebras systems, responsible for FPGA implementations that connect server nodes, cluster fabrics, and the wafer-scale engine (WSE).
The role covers architecture, RTL/bitstream implementation, performance optimization (bandwidth/latency), debug, and cross-team integration across current and future hardware generations.
Experience Level
Mid-level — candidates typically have multiple years of industry FPGA experience (see Education Requirements for degree-based alternatives).
Responsibilities
Primary responsibilities include owning IO architecture and delivering production FPGA solutions:
- Lead chassis-to-wafer IO architecture and design.
- Develop and improve RTL; implement next-generation FPGA designs and define future IO architectures.
- Produce production-ready bitstreams for deployment in large inference clusters.
- Work with design verification (DV) and board teams to prevent bugs, simplify debug, and execute board bring-up.
- Optimize datapaths and IO interfaces for bandwidth, latency, and fairness; diagnose and mitigate congestion and pause spreading.
- Drive network performance debugging in large AI clusters and integrate networking protocols and technologies.
- Lead cross-functional technical projects and coordinate across application, cluster architecture, and embedded software teams.
Requirements
Must-have technical skills and experience; education degree details are in Education Requirements below.
- Production FPGA experience: placement & routing, timing closure, simulation, and debug workflows and toolchains.
- Proficiency in Verilog and working in Git-based repositories.
- Experience producing production-ready bitstreams and supporting deployed clusters.
- Familiarity with network protocols (TCP, RoCE) and network analysis tools (e.g., Wireshark).
- Experience with RDMA/RoCE implementations or similar network IO stacks and performance optimization.
- Ability to collaborate with board, DV, software, and architecture teams for integration and bring-up.
- Nice-to-have: prior exposure to network switch environments (Arista, Juniper) and AI-augmented development tools.
Education Requirements
Either 5+ years of industry experience delivering production FPGA solutions, OR a Master’s or PhD in Computer Engineering or Electrical Engineering plus ~3 years of industry experience.
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.
