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FPGA Engineer

Connvertex Technologies
June 10, 2026
Full-time
On-site
San Francisco, California, United States
RTL Design Jobs, Level - Senior

Job Title

FPGA Engineer

Role Summary

Develop and verify RTL and digital logic for ASIC/FPGA projects with a focus on synthesis and timing closure. Work with EDA tools and system-level interfaces to deliver reliable silicon-level designs.

Position interacts with customers for status reporting and to ensure requirements are met.

Experience Level

Senior — requires extensive industry experience (guidance: 8+ years in ASIC or related work per employer guidance).

Responsibilities

The core responsibilities include:

  • Design and implement RTL (Verilog) for digital blocks and subsystems.
  • Perform synthesis and collaborate on timing closure.
  • Use EDA tools for CDC (clock-domain crossing) analysis and STA (static timing analysis).
  • Integrate and verify on-chip interconnects and protocols such as AMBA AXI and NoC.
  • Communicate technical status to customers; provide daily or weekly progress reports.
  • Ensure customer satisfaction through timely delivery and issue resolution.

Requirements

Must-have technical skills and experience:

  • Strong RTL design skills and solid understanding of digital design and synthesis flows.
  • Experience with EDA tools for CDC and STA.
  • Verilog design experience (approximately 5+ years on RTL/verification work recommended).
  • Familiarity with AMBA AXI and Network-on-Chip (NoC) architectures.
  • Customer-facing communication skills and experience reporting project progress.

Education Requirements

Requires a Bachelor's degree in Electrical Engineering or Computer Engineering with a minimum of 8 years of ASIC or related experience, or a Master’s degree in Electrical or Computer Engineering with at least 8 years of ASIC or related experience.


About the Company

Company: Connvertex Technologies

Connvertex Technologies logo

Date Posted: 2026-06-10