FPGA Engineer

Job Title

FPGA Engineer

Role Summary

Design and implement FPGA-based systems for medical devices, focusing on VHDL RTL development, verification, and system integration. Work on high-throughput, low-latency data acquisition and processing for diagnostic imaging and sensing subsystems as part of an Agile engineering team.

Experience Level

Mid-level. The role expects approximately 4–10 years of hands-on FPGA design experience with VHDL as the primary HDL.

Responsibilities

Primary responsibilities include architecture, RTL development, verification, and system bring-up for medical imaging and acquisition FPGA designs.

• Own FPGA RTL design using VHDL; develop reusable IP (state machines, controllers, DSP modules, memory interfaces).
• Implement deterministic, low-latency data paths for diagnostic imaging and acquisition systems.
• Translate system requirements into FPGA architecture with traceability.
• Implement and validate high-speed interfaces (JESD204B/C, LVDS, MIPI, SPI, I²C, UART).
• Design high-throughput acquisition and buffering pipelines using DDR4/DDR5 and AXI interconnects.
• Ensure timing, synchronization, and clocking across modalities (ultrasound, CT, MRI, sensing subsystems).
• Develop self-checking VHDL testbenches and perform block/system verification.
• Perform synthesis, place & route, timing analysis and closure; execute linting and CDC checks.
• Support lab bring-up and system debugging using ILA/SignalTap, oscilloscopes, logic and protocol analyzers.
• Contribute to regulatory documentation, requirements traceability, risk management, and verification artifacts for medical-device compliance.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 4–10 years hands-on FPGA design experience with VHDL as the primary HDL.
• Strong understanding of synchronous digital design: clocking, CDC/reset-domain considerations, timing analysis and closure.
• Experience with FPGA platforms (Xilinx/AMD or Intel) and the full FPGA toolflow.
• Proven ability to implement complex state machines, DSP blocks, and interface logic in VHDL.
• Familiarity with lab bring-up and FPGA system debugging.
• Experience developing verification environments and using simulators such as ModelSim/QuestaSim, Vivado Simulator, or Riviera-PRO.
• Competence with synthesis, P&R, timing closure; ability to optimize power and resource utilization.
• Practical experience with high-speed I/O and data acquisition interfaces and DDR memory systems.
• Nice-to-have: experience with medical-device standards and regulatory processes (FDA, EU MDR, ISO 14971, IEC 62304, IEC 60601) and familiarity with tools for requirements and risk traceability.

Education Requirements

Not specified.

About the Company

Company: EndoSec

Headquarters: Madison, WI, USA

Developer of hardware security solutions specializing in FPGA-based IP cores, cryptographic implementations, and embedded system integration for secure hardware and verification applications.