FPGA Development Tools Engineer – Synthesis

Job Title

FPGA Development Tools Engineer – Synthesis

Role Summary

Join the Synthesis team to develop and improve synthesis algorithms and toolchain integration that convert RTL into optimized gate-level implementations for FPGA platforms. The role focuses on quality-of-result (performance, power, area) and on integrating synthesis with placement, routing, and timing flows.

Work closely with architecture, STA, placement, routing, and validation teams to deliver scalable EDA tools and automation for complex RTL designs.

Experience Level

Senior — the position requests 10+ years of experience in FPGA/ASIC design, EDA tools, or related fields.

Responsibilities

Primary responsibilities include building synthesis capabilities, improving QoR, and enabling toolchain integration and automation.

• Design, implement, and optimize synthesis algorithms for Verilog/SystemVerilog/VHDL to gate-level mapping.
• Integrate synthesis with placement, routing, and static timing analysis stages of the compiler flow.
• Improve performance, power, and area through synthesis-driven optimizations and QoR enhancements.
• Analyze and transform complex RTL; develop analysis methodologies and tools.
• Debug synthesis results, investigate timing and logic-structure issues, and drive fixes to resolution.
• Develop internal tooling, scripts, and automation to improve flows and engineer productivity.
• Collaborate cross-functionally with silicon, architecture, STA, placement/routing, and validation teams.

Requirements

Must-have technical skills and experience required for the role.

• 10+ years of experience in FPGA/ASIC design, EDA tools, or related fields.
• Hands-on RTL expertise with Verilog/SystemVerilog or VHDL and synthesis flows.
• Proficiency in C/C++ for tool development.
• Strong understanding of algorithms and data structures; experience with debugging and performance analysis.
• Knowledge of logic synthesis and optimization techniques, and timing-driven design considerations.
• Familiarity with FPGA or ASIC design flows (synthesis → place & route → STA).
• Strong problem-solving skills; ability to analyze complex systems and deliver scalable solutions.

Nice-to-have

• Experience with synthesis tools or FPGA toolchains (Quartus, Vivado).
• Knowledge of FPGA architectures (LUTs, DSPs, BRAM, interconnect) and advanced optimizations (retiming, logic restructuring, resource sharing).
• Scripting experience (Python, Tcl) and background in compiler development or EDA algorithms.
• Experience working in large, distributed engineering teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; candidates with a PhD are encouraged. Relevant experience obtained during doctoral studies may count toward the required years of experience; equivalent practical experience is also considered.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.