FPGA Compiler (Placer) Engineer

Job Title

FPGA Compiler (Placer) Engineer

Role Summary

Develop and optimize FPGA placement algorithms within the compiler toolchain to improve performance, power, and quality of results for complex designs. Work on the Compiler team in San Jose, collaborating with routing, synthesis, timing, and architecture teams to integrate placement capabilities into the end-to-end FPGA compilation flow.

Experience Level

Mid-level — requires approximately 6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.

Responsibilities

Primary responsibilities focus on placement algorithm design, toolchain integration, and improving runtime and QoR for large designs.

• Design, implement, and improve FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Develop timing-driven and congestion-aware placement strategies for high-frequency designs.
• Improve runtime performance, scalability, and quality of results for large customer designs.
• Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.
• Collaborate with architecture, routing, synthesis, and STA teams to align placement with device constraints.
• Analyze placement quality, identify congestion and timing bottlenecks, and drive convergence and design closure improvements.
• Contribute to the end-to-end FPGA compilation flow and cross-team design reviews.

Requirements

Must-have technical skills and experience.

• 6+ years experience in FPGA/ASIC CAD, EDA tools, or closely related fields.
• Strong background in algorithms and data structures (optimization, graph theory, heuristics).
• Experience with placement algorithms and physical design flows (analytical placement, simulated annealing, partitioning, clustering).
• Proficient in C/C++ and software engineering best practices.
• Experience with timing-driven and congestion-driven optimization and ASIC/FPGA physical design methodologies.
• Proven ability to solve large-scale optimization problems with high performance and scalability requirements.

Nice-to-have:

• Experience with FPGA toolchains such as Quartus or Vivado.
• Knowledge of FPGA architectures, interconnect fabrics, routing, and timing-closure techniques.
• Experience with parallel or distributed algorithms for EDA tools.
• Scripting experience (Python, Tcl) for tooling and automation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.