FPGA Compiler (Placer) Engineer

Job Title

FPGA Compiler (Placer) Engineer

Role Summary

Join the Compiler team to design, implement, and optimize placement algorithms in the FPGA compiler toolchain. The role focuses on improving timing, congestion, and resource utilization for large, performance-critical designs on Altera FPGA architectures.

Experience Level

Mid-level — the posting requests 6+ years of relevant experience in FPGA/ASIC CAD, EDA tools, or related fields.

Responsibilities

Primary responsibilities center on placement algorithm development, integration with the compiler flow, and cross-team collaboration to improve quality of results and runtime.

• Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Contribute to the end-to-end FPGA compilation flow and integrate placement capabilities into the compiler infrastructure.
• Improve runtime performance, scalability, and quality of results for large customer designs.
• Develop and refine timing-driven placement strategies for high-frequency designs.
• Collaborate with architecture, routing, synthesis, and STA teams to align placement strategies with device constraints.
• Analyze placement quality, identify congestion and timing bottlenecks, and drive convergence and design closure improvements.
• Validate placement changes across diverse workloads and toolchain components.

Requirements

Must-have technical skills and experience for the role.

• 6+ years experience in FPGA/ASIC CAD, EDA tools, or related fields.
• Strong knowledge of algorithms and data structures (optimization, graph theory, heuristics).
• Experience with placement algorithms or physical-design flows (analytical placement, simulated annealing, partitioning, clustering).
• Proven experience with timing-driven and congestion-driven optimization techniques.
• Proficiency in C/C++ and software engineering best practices.
• Experience with ASIC or FPGA physical-design methodologies and solving large-scale optimization problems with performance and scalability constraints.

Nice-to-have / Preferred

• Experience with FPGA toolchains (e.g., Quartus, Vivado).
• Knowledge of FPGA architectures and interconnect fabrics; familiarity with routing and timing-closure techniques.
• Experience with parallel or distributed algorithms for EDA tools.
• Scripting experience for tooling and automation (Python, Tcl).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (as stated in the posting).

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.