FPGA/ASIC Design Engineer (Silicon Engineering)

Job Title

FPGA/ASIC Design Engineer (Silicon Engineering)

Role Summary

Develop RTL for next-generation FPGAs and ASICs used in Starlink satellite and ground systems. Work on SoC block design, integration, validation, and cross-functional coordination with systems, firmware, architecture, backend implementation and test teams.

This role focuses on delivering high-performance, power- and area-optimized silicon that operates in lab and on-orbit environments.

Experience Level

Entry-level. Requires approximately 1+ years of professional RTL design experience.

Responsibilities

Primary responsibilities include design, integration, and validation across the ASIC/FPGA lifecycle.

• Design ASICs and/or FPGAs, implementing SoC blocks and integration using Verilog/SystemVerilog (or Verilog/VHDL).
• Optimize designs for power, performance, and area.
• Participate across the full design lifecycle: architecture, microarchitecture, partitioning, and collaboration with backend/implementation teams.
• Support lab bring-up and hardware validation, including test systems for FPGA/ASIC verification and interoperability.
• Build tools and analyses to evaluate on-orbit and lab-collected data to improve designs.
• Collaborate with software and firmware teams to develop production software for silicon features.

Requirements

Must-have technical skills are listed first, followed by preferred skills.

Must-have:

• Professional RTL design experience with SystemVerilog, Verilog, or VHDL.
• Practical experience with ASIC or FPGA design and SoC integration (design or implementation exposure).
• Ability to work in a cross-functional engineering environment and contribute to lab validation and bring-up.
• Willingness to work extended hours or weekends as needed for mission-critical deadlines.
• ITAR eligibility as required (U.S. citizen, lawful permanent resident, refugee, asylee, or eligible for required State Department authorizations).

Nice-to-have / Preferred:

• ASIC/FPGA system integration experience and familiarity with SoC-level issues.
• Experience with Python, C/C++, and Bash for automation and tooling.
• Experience designing DSP or digital communications datapath blocks, modem design, or related signal-processing IP.
• Familiarity with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (SpyGlass), and FPGA toolchains (Vivado, Quartus).
• Understanding of AXI/AHB/APB or similar bus protocols.
• Experience debugging complex PCBs with oscilloscopes, spectrum analyzers, and lab instrumentation.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics. Preferred: Master's degree in Electrical/Computer Engineering or a related field.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.