Formal Verification Senior Engineer
QualcommJob Title
Formal Verification Senior Engineer
Role Summary
Responsible for formal property verification of GPU/graphics RTL blocks. The role writes assertion-based verification testbenches, develops and executes formal verification plans, debugs RTL artifacts, and drives formal sign-off in collaboration with global RTL and design-verification teams.
Experience Level
Senior-level role. The posting specifies typical ASIC/verification experience expectations (e.g., 2+ years in formal verification with relevant ASIC experience; alternative qualification paths listed in Education Requirements).
Responsibilities
Primary duties include planning and executing formal verification activities and coordinating with design teams to close verification gaps.
- Develop formal property verification (FPV) test plans and assertion-based verification testbenches.
- Author SystemVerilog Assertions (SVA) and use formal tools to prove properties and resolve proof complexity.
- Debug RTL artifacts uncovered by formal runs and work with RTL/DV teams to implement fixes.
- Apply abstraction and other techniques to reduce proof complexity and achieve sign-off.
- Drive coverage closure, track metrics, and produce formal sign-off matrices.
- Collaborate with global GPU RTL design and DV teams to meet project milestones.
- Document findings, mentor peers as needed, and communicate status to stakeholders.
Requirements
Core technical skills and experience required; equivalent practical experience considered.
- Hands-on experience in formal property verification (FPV) and developing assertion-based testbenches.
- Proficiency writing SystemVerilog Assertions (SVA) and using industry formal tools (examples: JasperGold, VC Formal).
- Ability to diagnose and debug RTL issues revealed by formal analysis.
- Experience applying abstraction and other techniques to manage formal proof complexity.
- Experience driving coverage closure and delivering formal sign-off matrices.
- Familiarity with other formal applications (DPV, C2RTL SEQ, RTL2RTL SEQ) is a plus.
- Prior exposure to GPU/3D graphics pipeline or GPU architecture is strongly preferred.
- Strong verbal and written communication skills and ability to work in cross-site teams.
Education Requirements
Minimum: Bachelor's degree in Science, Engineering, or related field plus 2+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field plus 1+ year of relevant experience; OR PhD in Science, Engineering, or related field. Preferred: Bachelor's or Master's in Electronics/Computer Engineering. Applications with equivalent practical experience will be considered.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
