Formal Verification Engineer - DV

Job Title

Formal Verification Engineer - DV

Role Summary

Join the ASIC Design Verification team to lead formal verification across custom IP, interface IP, and SoC subsystems that power Etched's inference-focused ASICs. The role focuses on proving design correctness, exposing corner-case bugs, and improving verification closure for compute arrays, DMA engines, NoCs, memory, PCIe, Ethernet, CPU subsystems, and vendor IP wrappers.

You will collaborate closely with architects, RTL designers, DV engineers, emulation, and software/firmware teams to develop formal properties, drive proofs to convergence, and contribute to formal sign-off methodology.

Experience Level

Mid-level — typically requires 5+ years of design verification experience with significant hands-on formal verification exposure.

Responsibilities

Primary responsibilities focus on defining formal strategy, authoring formal properties and environments, driving proofs to closure, and integrating formal work into the broader verification flow.

• Define and drive formal verification strategy for complex IP blocks, interface subsystems, and SoC integration logic.
• Develop formal verification plans covering correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
• Build reusable formal environments: SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction and reference models.
• Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, bounded proofs, and coverage metrics.
• Translate design intent and specifications into high-value formal properties and closure criteria with architects and RTL designers.
• Integrate formal work with UVM DV, emulation, software, and firmware regressions and coverage efforts.
• Debug complex RTL, protocol, datapath, connectivity, and integration bugs using counterexamples and waveform analysis.
• Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.

Requirements

Must-have technical skills and experience for immediate contribution. Strong candidates may have additional domain-specific experience listed separately.

• 5+ years of design verification experience, including substantial hands-on formal verification on complex digital designs or shipping silicon.
• Proficiency with SystemVerilog and SystemVerilog Assertions (SVA) and formal verification methodology.
• Experience with commercial formal tools (examples: Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal).
• Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces (PCIe, Ethernet, AXI/AMBA, etc.).
• Ability to model complex behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
• Proven debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.
• Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.
• Comfort working in a fast-paced startup environment and owning ambiguous, high-impact verification problems.

Nice-to-have:

• Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, or low-power controllers.
• Protocol compliance, register verification, reset verification, deadlock/livelock analysis, and vendor IP integration experience.
• Sequential LEC, arithmetic proofs, cache coherency checks, interrupt handling, or MMIO verification.
• Scripting for automation and debug in Python, TCL, Perl, or similar.

Education Requirements

Not specified.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.