Job Title
Formal Verification Engineer - CPU Core
Role Summary
Join the US CPU verification team to verify next-generation CPU cores using a combination of dynamic and formal verification techniques. The role focuses on ensuring correctness of architecture and microarchitecture changes for cores used in AI and high-performance compute workloads.
The engineer will contribute to verification strategy, own or lead formal verification efforts for microarchitecture blocks, and collaborate with RTL designers, architects, and global verification teams.
Experience Level
Mid-level. The posting requires professional verification experience; minimum experience guidance in the posting indicates candidates typically have 1–3+ years of relevant industry experience depending on degree level.
Responsibilities
Primary responsibilities include planning, creating, and executing verification work for CPU cores using dynamic and formal methods.
- Develop and execute verification test plans for architecture and microarchitecture changes.
- Design and implement pre-silicon verification collateral such as behavioral checkers, coverage monitors, test generators, and scoreboards.
- Own or lead formal verification for microarchitecture blocks or verification methodology components.
- Define formal verification strategy and perform ROI analysis to balance formal and dynamic validation techniques.
- Debug failing tests, perform root-cause analysis, and work with designers/architects to resolve issues.
- Analyze coverage gaps and create strategies to improve verification completeness.
- Collaborate with global RTL, architecture, dynamic verification, and formal teams to drive verification methodologies and execution.
- Produce rigorous, stress-inducing tests to expose subtle bugs and validate design robustness.
Requirements
Must-have technical skills and experience required to perform the role.
- In-depth computer architecture knowledge, especially out-of-order execution, memory hierarchy, and memory management.
- Experience with hardware modeling languages and simulation tools (Verilog, VHDL, SystemVerilog, or equivalent).
- Assertion writing, checker development, coverage analysis, failure debug, and root-cause analysis experience.
- Proficiency in at least one programming language (C/C++, Java, Specman E) and familiarity with scripting languages (Perl, Python, Ruby, TCL).
- Experience in pre-silicon verification of CPU cores with areas of technical ownership or demonstrated expertise relevant to CPUs.
- Experience with industry-standard formal verification tools such as JasperGold, IFV, Questa Formal, or VC Formal.
- Strong problem-solving skills and tolerance for ambiguity; ability to work across teams and drive verification closure.
Nice-to-have:
- Knowledge of Intel Architecture ISA and x86 assembly language.
- Pre- and post-silicon debug and analysis experience.
- Evidence of technical innovation (research publications, patents) or advanced validation methodology work.
- Experience applying sequential equivalence checking and formal abstractions/complexity reduction techniques.
Education Requirements
Minimum qualifications specify a Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related STEM field plus 2+ years relevant experience, OR a Master’s degree in those fields plus 1+ year relevant experience. Equivalent practical experience in related technical verification roles is implicitly acceptable where noted.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.

Date Posted: 2026-05-06