Field Application Engineer, Verification

Job Title

Field Application Engineer, Verification

Role Summary

Work with semiconductor customers in the region to deploy and optimize verification tools and methodologies, debug complex RTL signoff issues, and ensure projects meet verification and tapeout milestones. Part of the Customer Success Group collaborating with R&D, product validation, and account teams.

Experience Level

Mid-level — typically 3–5 years of hands-on industry experience in ASIC design or verification.

Responsibilities

Provide technical leadership and hands-on support to customer design teams to accelerate verification signoff and reduce respins.

• Deploy and optimize verification solutions across customer flows (VC SpyGlass, VCS, VC LP, VC Formal, Verdi).
• Debug RTL signoff issues: CDC violations, lint errors, RDC problems, UPF conflicts, and formal property failures.
• Develop reproducible test cases, repeatable methodology improvements, and reference flows with R&D and product validation.
• Lead technical engagements during critical project phases, onsite or remote, to help customers meet tapeout schedules.
• Gather customer requirements, translate design challenges into flow improvements, and prioritize fixes with product teams.
• Train customer engineering teams on verification methodologies, tool usage, and best practices.
• Coordinate with account and technical account managers to drive tool adoption and support business growth.

Requirements

Practical verification and signoff expertise, strong RTL skills, and the ability to debug and communicate effectively across customers and internal teams.

Must-have:

• 3–5 years industry experience in ASIC design or verification.
• Strong command of VHDL, Verilog, and SystemVerilog RTL and a solid understanding of RTL-to-tapeout flows.
• Proven experience with RTL signoff flows: linting, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and property checking (static and formal).
• Hands-on low-power verification experience using UPF or CPF and debugging power-intent issues.
• Experience with simulation and verification methodologies: directed tests, constrained-random testing, assertions, coverage-driven verification, and gate-level simulation.
• Ability to create minimal reproducible test cases, write scripts, and work closely with R&D to resolve tool issues.

Nice-to-have:

• Familiarity with Synopsys tools such as VC SpyGlass, VCS, VC LP, VC Formal, FishTail, or Verdi.
• Experience influencing product roadmaps or developing methodologies that scale across projects.
• Comfort working across global teams and time zones and conducting onsite customer engagements during critical phases.

Education Requirements

BE/BTech or ME/MTech in Electronics Engineering, Computer Science, or Microelectronics.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.