Applications Engineering, Sr Engineer

Job Title

Applications Engineering, Sr Engineer

Role Summary

Senior applications engineer responsible for leading VCS simulation deployments at customer sites. Partner with customers, field application engineers, and R&D to diagnose verification issues, integrate simulators into customer flows, and drive product improvements based on real-world deployments.

Experience Level

Senior — expects multiple years of verification experience (see Education Requirements for hiring guidance).

Responsibilities

Lead customer engagements to ensure successful simulation and verification delivery.

• Lead VCS simulation deployments, integrate tools into customer flows, and remove adoption blockers.
• Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues.
• Collaborate with field application engineers and R&D to translate customer pain points into product fixes and validate those fixes.
• Conduct competitive evaluations and benchmarking to build the technical case for adoption.
• Develop automation and tooling using Perl, TCL, Shell, and Make to improve simulation throughput and reduce manual work.
• Support advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows.

Requirements

Essential technical skills and proven experience required for this role.

• Deep hands-on experience with simulation technologies (VCS or equivalent) and an understanding of event-driven simulation internals.
• Proficiency in SystemVerilog, UVM, SVA, and HDLs such as Verilog and VHDL; able to read and debug complex testbenches and RTL.
• Proven track record debugging simulation mismatches, performance issues, and verification flow problems in production customer environments.
• Strong scripting skills in Perl, TCL, Shell, and Make to automate workflows and build productivity tools.
• Working knowledge of UNIX/Linux environments, version control systems, and large-scale verification infrastructure.
• Experience interfacing with product validation and R&D to propose and validate improvements based on field feedback.
• Nice-to-have: experience with Verdi, exposure to low-power simulation, gate-level verification, and functional safety methodologies.

Education Requirements

Bachelor's degree in Electronics or Computer Engineering with 5+ years of relevant experience, or a Master's degree with 3+ years of relevant experience; focus on digital design verification. (This is the employer's stated hiring guidance.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.