FEOL RET Process Development Engineer

Job Title

FEOL RET Process Development Engineer

Role Summary

The FEOL RET Process Development Engineer will develop and implement resolution enhancement and retargeting strategies to translate customer design intent into manufacturable layouts for advanced nodes (for example 28nm and 22nm). The role sits in the RET (Resolution Enhancement Team) and works closely with OPC, lithography, process integration, and EDA teams to improve printability, yield, and manufacturability.

Experience Level

Mid-level. The posting specifies approximately 5+ years of relevant experience in design retargeting, OPC, or physical design in a semiconductor or EDA environment.

Responsibilities

Key responsibilities include:

• Develop and implement design retargeting strategies to align layouts with process capabilities.
• Collaborate with OPC, lithography, and process integration teams to ensure accurate pattern transfer and high yield.
• Analyze and modify layout geometries to improve printability and process-window robustness.
• Automate retargeting flows using EDA tools and integrate them into the tape-out pipeline.
• Support customer design enablement by providing feedback on layout constraints and manufacturability guidelines.
• Perform data analysis using CD metrology, SEM review, and simulation results to refine retargeting rules.
• Contribute to development of design rules and patterning strategies for advanced nodes.
• Mentor junior engineers and share knowledge within the team.

Requirements

Must-have qualifications and skills:

• 5+ years of experience in design retargeting, OPC, or physical design in a semiconductor or EDA environment.
• Strong understanding of optical lithography principles and RET techniques (OPC, SRA, assist features) and mask technology.
• Hands-on experience with industry OPC/lithography tools (examples: Synopsys Sentaurus Lithography, Mentor Calibre, ASML Brion).
• Proficiency in scripting to automate flows (any scripting language).
• Familiarity with layout editing and verification tools (examples: Calibre, Virtuoso, ICC2).
• Understanding of lithography, patterning, and process-integration challenges at advanced nodes; familiarity with 28nm and below.

Nice-to-have:

• Experience in analog layout interaction with lithography and OPC flows.
• Experience with statistical data analysis and yield-improvement methodologies.
• Knowledge of DRC/LVS and Design Technology Co-Optimization (DTCO).
• Exposure to machine-learning or data-driven approaches for layout optimization.
• Strong cross-functional communication and teamwork skills.

Education Requirements

Master's degree required in Electrical Engineering, Physics, Materials Science, or a related field. PhD in a related field is preferred. (The posting lists a Master's as the required degree and a PhD as preferred.)

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.