FE Engineering

Job Title

FE Engineering

Role Summary

Work on logic synthesis and optimization for Apple graphics IP delivered to silicon. The engineer will focus on synthesis, equivalence, DFT/ATPG, lint, and timing to meet power, performance, and area (PPA) targets for Apple GFX partitions.

The role partners closely with RTL, physical design, STA, DFT, CAD, and vendor teams to deliver production-quality netlists and signoff-ready designs. Typical schedule: 40 hours/week.

Experience Level

Entry-level / Early Career - the posting specifies a Master’s degree plus 1 year of relevant experience.

Responsibilities

The engineer will be responsible for synthesis, verification, and optimization tasks including:

• Perform logic synthesis and physical synthesis to meet PPA (power, performance, area) targets for graphics IP.
• Analyze and debug RTL (Verilog/SystemVerilog) and gate-level netlists; ensure logical equivalence.
• Run formal equivalence checks and static timing analysis (STA) and resolve timing violations.
• Ensure designs are Lint clean and have properly inserted DFT chains with acceptable test coverage.
• Execute and verify Engineering Change Orders (ECOs) at the gate-level netlist.
• Collaborate with RTL, physical design, STA, DFT, CAD, and vendor teams to resolve issues and improve design quality.
• Develop and run experiments and flows to improve QoR; analyze synthesis and STA reports.
• Automate flows and create utilities (scripting) to improve productivity and design quality.
• Perform signoff checks and validate that designs meet release criteria.

Requirements

Must-have technical skills and practical experience (education requirements are listed separately below):

• Experience performing physical synthesis to optimize digital designs for PPA trade-offs.
• Experience analyzing and debugging RTL described in Verilog or SystemVerilog at the RTL level.
• Experience performing formal logic equivalence verification between RTL and gate-level netlists.
• Experience performing static timing analysis (STA) and debugging timing violations on critical paths.
• Experience developing scripts in Python, Perl, or Tcl to automate flows, extract data, and generate reports.
• Experience implementing and verifying functional and timing ECOs at the gate-level netlist.
• Experience analyzing designs with multiple power domains defined by UPF.
• Familiarity with DFT/ATPG flows and ensuring test coverage is acceptable.

Education Requirements

Master's degree (or foreign equivalent) in Electrical Engineering or a related field, plus 1 year of relevant experience. The posting specifies a Master’s degree explicitly; no alternative degree or "or equivalent experience" language was provided.

About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.