FCT PD Lead

Job Title

FCT PD Lead

Role Summary

Lead Full Chip Timing (FCT) execution and timing signoff activities within the Physical Design organization for complex SoC and subsystem designs. Work cross-functionally with Architecture, Design, PD, STA, DFT, CAD and methodology teams to achieve timing closure and first-pass silicon success.

Experience Level

Senior — typically 14+ years of experience in Physical Design, Static Timing Analysis, constraints development and timing signoff preferred.

Responsibilities

Accountable for end-to-end timing closure and signoff across integration projects and delivery stages.

• Lead the Full Chip Timing team for timing constraints development and signoff.
• Own timing closure from synthesis through placement, CTS, routing and post-route ECO.
• Define, develop and validate SDC constraints, clocks and timing methodologies.
• Partner with Architecture and STA to set timing budgets, statistical targets and signoff criteria.
• Analyze and manage advanced-node timing margins (LVF, SSTA, OCV/AOCV/POCV) and variation-aware signoff.
• Plan and execute timing ECOs to meet tapeout schedules.
• Collaborate with CAD and EDA vendors to improve timing flows, automation and tools.
• Mentor engineers and provide technical leadership across multiple programs.

Requirements

Must-have technical skills, tools and leadership experience for this role; listed preferences are labeled.

• Must-have: Extensive experience in Full Chip Timing closure and STA signoff for SoC-level designs.
• Must-have: Expertise in timing constraints (SDC) and timing ECO methodologies.
• Must-have: Hands-on experience with Synopsys PrimeTime (PT) and gate-level timing analysis (GCA).
• Must-have: Strong understanding of floorplanning, placement, CTS and routing interactions with timing.
• Must-have: Proficiency in scripting for automation (Tcl, Perl, Shell, Python).
• Must-have: Proven ability to lead cross-functional teams and mentor engineers on timing closure.
• Nice-to-have: Experience with Fusion Compiler and/or ICC2.
• Nice-to-have: Knowledge of MCMM timing analysis, DFT timing and MBIST timing verification.
• Nice-to-have: Experience improving timing closure flows with EDA vendors and CAD teams.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.