Job Title
Expert Hardware/RTL Engineer - SystemVerilog/Verilog
Role Summary
Evaluate real-world RTL engineering work and produce concise, expert written assessments that judge code quality, correctness, and engineering practice. Work is task-based, time-bounded, and executed inside containerized repositories with automated/CI checks.
Your assessments will directly influence how AI systems are trained to reason about hardware design.
Experience Level
Senior β typically 5+ years professional or research RTL experience in SystemVerilog or Verilog.
Responsibilities
Perform expert reviews of RTL work and document clear, evidence-based evaluations.
- Assess technical tasks against professional standards and explicit evaluation criteria.
- Review and analyze RTL code (SystemVerilog/Verilog) and testbench/UVM implementations.
- Run and interpret programmatic and CI-style checks inside Docker-based repositories.
- Provide precise, structured written rationales explaining judgments and recommendations.
- Complete well-defined, time-bounded tasks; manage variable task flow and occasional weekend availability.
Requirements
Key qualifications and environment expectations.
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Must-have: 5+ years hands-on RTL experience in SystemVerilog or Verilog; strong RTL design and verification fundamentals.
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Must-have: Practical experience with testbench/UVM, FPGA or ASIC flows, and common EDA toolchains (examples: Vivado, Quartus, Synopsys, Cadence).
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Must-have: Comfortable working in Linux/Docker environments and reading automated/CI checks, or able to ramp quickly.
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Must-have: Ability to explain not only what code does but why it is correct or idiomatic in clear writing.
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Nice-to-have: Background in semiconductor, telecom, defense/aerospace, national labs, or academic research; prior FPGA/ASIC delivery experience.
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Engagement details: Hourly compensation range $110β$190/hour; expected commitment 20β40 hours/week; tasks arrive in variable batches.
Education Requirements
Not specified.
About the Company
Company: Lumiere Systems
Engineering services firm specializing in semiconductor and ASIC design and verification for ARM-based SoCs. Engages in full verification lifecycle (UVM/SystemVerilog, formal, gate-level simulation) and collaborates with global verification teams and client partners.

Date Posted: 2026-06-05