Experienced RTL Engineer with Verilog Focus

Job Title

Experienced RTL Engineer (Verilog focus)

Role Summary

Senior RTL engineer responsible for RTL design, verification and debugging using Verilog HDL for complex SoC projects. The role interfaces with architecture, synthesis and backend teams to support physical realization of designs.

The position focuses on drafting microarchitecture guidelines, implementing RTL from specifications, and ensuring design correctness through simulation and collaboration with physical design teams.

Experience Level

Senior — requires 10+ years of relevant professional experience.

Responsibilities

Primary responsibilities include:

• Perform RTL design and debugging using Verilog HDL.
• Analyze architectural specifications and translate them into RTL for SoC projects.
• Draft microarchitecture and functional guidelines for new and updated features.
• Collaborate with synthesis, backend and physical-design teams to support timing-closure and implementation.
• Execute simulations and verification to validate design behavior and correctness.

Requirements

Must-have technical skills and experience:

• Minimum 10 years of relevant professional experience in RTL or chip design.
• Expertise in Verilog HDL and RTL coding practices.
• Strong understanding of System-on-Chip methodology.
• Familiarity with physical design processes and implementation constraints.
• Experience working with synthesis and backend flows and supporting timing/debug cycles.
• Proven ability to run simulations and debug complex RTL issues.

Education Requirements

Bachelor's or Master's degree in Computer Engineering.

About the Company

Company: Infotree Global Solutions

Staffing and IT services firm specializing in global recruitment, workforce solutions, and technology consulting for engineering and software development roles.