Engineering Program Manager, RISC-V
TenstorrentJob Title
Engineering Program Manager, RISC-V
Role Summary
Lead program management for a high-performance RISC-V CPU, coordinating architecture, design, verification, physical design, and DFT from specification through tapeout and post-silicon debug. You will align cross-functional teams, set milestones, manage risks, and report progress to senior leadership.
Position is hybrid and based out of Austin, TX or Santa Clara, CA.
Experience Level
Mid-level (typical). Tenstorrent welcomes candidates at various experience levels; final level and offer will be determined during the interview process.
Responsibilities
You will drive execution and delivery of CPU development programs and coordinate technical teams and stakeholders.
- Own full lifecycle CPU program management: specification, design, tapeout, and post-silicon debug.
- Define scope, schedule, resource allocation, and success criteria; maintain and update project plans.
- Coordinate architecture, RTL design, verification, physical design, and DFT teams to meet milestones.
- Identify and manage technical and schedule risks; define mitigation and contingency plans.
- Lead design reviews, status reporting, and executive-level communications on metrics and risks.
- Drive schedule trade-offs and technical decision-making with engineering leads.
- Support post-silicon bring-up, debug prioritization, and cross-team remediation efforts.
Requirements
Must-have qualifications and technical skills required to perform the role; items labelled "Nice-to-have" are preferred but not required.
- Proven experience managing silicon or SoC development programs and delivering complex hardware milestones.
- Technical background in CPU, SoC, or silicon development with hands-on familiarity with design and verification flows.
- Experience owning schedules, resourcing, and cross-functional execution across architecture, design, verification, physical, and DFT teams.
- Experience with post-silicon debug and supporting silicon bring-up activities.
- Strong verbal and written communication skills for engineering and executive audiences.
- Demonstrated ability to identify risks, drive mitigation plans, and make trade-offs under schedule pressure.
- Nice-to-have: Functional Safety (ISO 26262) experience and knowledge of automotive hardware requirements.
- Nice-to-have: Prior experience with RISC-V CPU IP, tapeout processes, or customer-facing delivery of IP/products.
Education Requirements
Not specified.
About the Company
Company: Tenstorrent
Headquarters: Austin, Texas, United States
Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.
